Introduction: Bridging Design and Manufacturing

You've written RTL, simulated it thoroughly, and verified it works correctly. But here's a fundamental question: how does your abstract hardware description—registers, wires, logic operations—become actual transistors and metal wires on a silicon chip? The answer lies in the Process Design Kit (PDK), the crucial bridge between the logical world of RTL and the physical world of semiconductor fabrication.

Understanding PDKs is essential for anyone serious about chip design. While you might not interact with PDK details daily when writing RTL, knowing what's "under the hood" helps you write better, more synthesizable code and understand the constraints and tradeoffs that drive hardware design decisions. The Skywater 130nm PDK represents a historic milestone: the first fully open-source PDK for a manufacturable process, democratizing chip design in ways previously unimaginable.

In this module, we'll demystify PDKs, explore what the Skywater 130nm process offers, and clarify the often-confusing relationship between technology node names and actual transistor dimensions.

What is a Process Design Kit?

A Process Design Kit is a comprehensive collection of files, models, and documentation that describes everything a designer needs to know about a specific semiconductor manufacturing process. Think of it as the "owner's manual" for a fabrication technology—it tells you what's physically possible to build and provides the tools to design within those constraints.

The Components of a PDK

A complete PDK contains multiple interconnected components:

Technology Files: These describe the physical layers available in the process—how many metal layers for routing, what thicknesses, what materials. They also specify design rules: minimum wire widths, spacing between features, via sizes, and thousands of other geometric constraints that ensure your design can actually be manufactured.

Standard Cell Libraries: These are pre-designed, pre-characterized logic gates and flip-flops. Instead of designing transistors directly, you use these standard cells as building blocks. A typical library contains:

• Basic gates (AND, OR, NAND, NOR, XOR, inverters)
• Complex gates (AND-OR-INVERT, OR-AND-INVERT combinations)
• Flip-flops and latches (various types with different features)
• Buffers and clock cells
• Special cells (scan flip-flops, delay cells, power switches)

Each cell comes with multiple views: layout (physical geometry), schematic (transistor-level circuit), abstract (simplified for place-and-route tools), timing models (how fast signals propagate), and power models (how much current they draw).

I/O Libraries: Real chips need to communicate with the outside world. I/O (Input/Output) libraries provide special cells called "pads" that handle the interface between the chip's internal logic (operating at low voltages like 1.8V) and external signals (which might be 3.3V, 5V, or other voltages). These pads include:

• Input buffers with protection circuits
• Output drivers with controlled slew rates
• Bidirectional pads for buses
• Power and ground pads
• Special pads (analog, high-speed, ESD protection)

Device Models: For circuit simulation (SPICE), the PDK provides detailed electrical models of transistors, resistors, capacitors, and other devices. These models capture how devices behave across voltage, temperature, and process variations. They're essential for analog design and for verifying that digital circuits meet timing under worst-case conditions.

Design Rule Manuals: Comprehensive documentation explaining every constraint and requirement. These can run hundreds of pages, covering everything from minimum transistor lengths to metal density rules to antenna effect prevention.

Verification Decks: Scripts for tools that check your design against manufacturing rules. DRC (Design Rule Check) ensures geometric correctness. LVS (Layout Versus Schematic) verifies that physical layout matches the intended circuit. These automated checks catch errors before expensive fabrication.

Technology Libraries for EDA Tools: Formatted files that allow synthesis tools (like Yosys), place-and-route tools (like OpenROAD), and verification tools to work with the process. These include timing libraries (.lib format), physical libraries (.lef format), and technology configuration files.

Why PDKs Were Historically Closed

Traditionally, semiconductor foundries (companies that manufacture chips, like TSMC, GlobalFoundries, Intel) kept PDKs highly confidential, requiring Non-Disclosure Agreements (NDAs) and expensive licensing. Several factors drove this secrecy:

Competitive Advantage: PDK details reveal manufacturing capabilities and techniques that represent billions of dollars in research and development.

IP Protection: Standard cell libraries are valuable intellectual property, optimized over years.

Customer Relationships: Foundries wanted direct relationships with serious customers (typically large companies or well-funded startups) rather than supporting hobby designers or small academic projects.

Liability Concerns: Making PDKs widely available might lead to misuse or designs that fail, potentially damaging the foundry's reputation.

This secrecy created a massive barrier to entry. You couldn't learn real chip design without industry connections or enrollment in specific university programs with foundry partnerships.

The Skywater 130nm Revolution

In 2020, everything changed. Google, working with Skywater Technology Foundry, released the Skywater 130nm PDK under the Apache 2.0 open-source license. For the first time, anyone could download a complete, manufacturable PDK without NDAs, fees, or restrictions.

What Makes This Historic

This wasn't just incremental progress—it was transformative:

True Accessibility: Anyone with an internet connection can access professional-grade manufacturing data for actual silicon. Students, hobbyists, researchers, and startups can now learn and experiment with real technology.

Complete Ecosystem: The release included not just basic documentation but full standard cell libraries, I/O cells, memory compilers, and all supporting files needed for complete chip design.

Manufacturing Access: Through programs like Google's ChipIgnite (now continued by Efabless), designers can have their open-source designs fabricated for free. This completes the loop from learning to actual silicon.

Tool Development: Open PDKs enable development of open-source EDA tools. Previously, tool developers couldn't test with real foundry data. Now, tools like OpenROAD, Magic VLSI, and others can be developed and validated against actual manufacturing technology.

Education Revolution: Universities worldwide can now teach complete chip design flows using real manufacturing processes, not just simplified academic models.

The Skywater 130nm Process: Technical Overview

Let's understand what the Skywater 130nm process actually offers.

Technology Basics: The 130nm refers to the minimum gate length—the smallest transistor channel dimension the process can reliably manufacture (though as we'll discuss shortly, "130nm" is more marketing than physics at this point).

Metal Layers: The process provides five metal layers for interconnect:

• M1 (Metal 1): Thinnest, closest to transistors, highest resistance
• M2-M4: Intermediate layers for local and semi-global routing
• M5: Thickest, lowest resistance, for global signals and power distribution

More metal layers mean more routing flexibility. Five layers is adequate for medium-complexity digital designs and many analog circuits.

Voltage Options: The process supports multiple voltage domains:

• 1.8V core logic: Standard digital logic operates here
• 3.3V I/O: For interfacing with external components
• 5.0V I/O: For legacy interfaces or higher-voltage applications

This multi-voltage capability is essential for practical chips that must interface with various systems.

Device Options: Beyond basic transistors, the process provides:

• Multiple threshold voltages: Low-VT (fast but leaky), standard-VT (balanced), high-VT (slow but low leakage)
• I/O transistors: Thicker oxide devices that handle higher voltages
• Resistors and capacitors: For analog circuits, RC filters, bias networks
• ESD protection devices: To prevent electrostatic discharge damage
• RF devices: Inductors and varactors for radio-frequency applications

This variety enables mixed-signal designs combining digital, analog, and RF functionality on a single chip.

Standard Cell Library: The open-source standard cell library includes over 300 different cells optimized for different scenarios:

• Multiple drive strengths (cells optimized for driving small vs. large loads)
• Different versions of common gates (space-optimized vs. speed-optimized)
• Sequential elements with various features (scan, set/reset, enable)
• Clock tree cells (buffers with balanced rise/fall times)
• Filler cells and decoupling capacitors

This comprehensive library allows synthesis tools to optimize for area, speed, or power as priorities dictate.

Technology Node vs. Actual Feature Size: Clearing the Confusion

Here's where chip design gets confusing: the "130nm" name doesn't mean everything on the chip is 130 nanometers. In fact, much is larger. Let's demystify technology node naming.

Historical Context

Originally, technology node names corresponded to actual transistor gate lengths. In the 1990s, a "500nm process" really did have 500nm-long transistor gates. Similarly, early definitions used the half-pitch (the distance from the center of one metal line to the center of the adjacent line) as the node name.

This made sense and was reasonably honest. A smaller number meant genuinely smaller, denser transistors and tighter metal pitch, enabling more transistors per chip and potentially higher speeds due to shorter wires.

When Marketing Took Over

As processes scaled below 90nm, the correlation between node names and actual physical dimensions began breaking down. Why? Several factors:

Physics Gets Weird: As features shrink toward atomic scales, quantum effects and other phenomena make simple scaling impossible. Different parts of the transistor scale at different rates.

Multi-Patterning: Below about 20nm, traditional lithography can't create the desired features directly. Instead, multiple exposures and processing steps build up the pattern. The "node name" refers to the effective density, not the lithography wavelength.

Marketing Pressure: Foundries compete intensely. Announcing a "7nm" node sounds better than "10nm," even if the actual improvement is more modest. Node names became marketing brands more than technical specifications.

No Standard Definition: Different foundries measure different things. One company's "7nm" might be equivalent to another's "10nm." There's no independent arbiter of what a node name means.

What Does "130nm" Actually Mean for Skywater?

For the Skywater process:

Minimum Gate Length: The smallest transistor channel length that can be reliably manufactured is approximately 130nm. This is the feature that gives the node its name.

Metal Pitch: The actual spacing between metal wires varies by layer:

• M1 (bottom layer): ~340nm minimum pitch
• M5 (top layer): ~1.6μm minimum pitch

These are much larger than 130nm because metal layers have different rules than transistor gates.

Transistor Density: You can fit roughly 50,000 to 100,000 transistors per square millimeter, depending on design style. Modern 5nm processes achieve 100-300 million transistors per mm²—a 1000-10,000x difference.

Feature Sizes in Context: Many features are larger than the node name suggests:

• Standard cell heights: 2.72μm (over 20x the "130nm" name)
• Minimum wire width on M1: 140nm (similar to the node name)
• Via sizes: 170nm × 170nm

So "130nm" is a rough guide to the smallest features possible, not a description of everything on the chip.

Why 130nm is Perfect for Learning and Many Applications

While not cutting-edge, 130nm is far from obsolete:

Mature and Reliable: The process is well-understood with excellent yield. Decades of manufacturing experience mean fewer surprises.

Cost-Effective: Older process nodes are cheaper to manufacture. For low-to-medium volume production, 130nm can be more economical than advanced nodes.

Sufficient for Many Applications: Not every chip needs billions of transistors. Microcontrollers, sensor interfaces, power management ICs, analog circuits, and many other devices work perfectly well in 130nm.

Real-World Use Cases:

• Automotive electronics (where reliability matters more than density)
• Medical devices
• IoT sensors and edge computing
• Industrial control systems
• Audio/video processing
• Power management
• Communication protocols (Bluetooth, Zigbee, etc.)

Educational Value: 130nm is complex enough to teach real chip design challenges (timing closure, power distribution, routing congestion) but not so complex that it's overwhelming. You can actually understand what's happening physically.

Open Availability: Most importantly, you can actually access it! Leading-edge processes (5nm, 3nm) require massive NDAs, expensive access fees, and relationships with foundries. Skywater 130nm is free and open.

The Practical Impact: What This Means for Your Designs

Understanding PDKs and the Skywater 130nm process has direct implications for how you write and optimize RTL:

Area Considerations: While 130nm isn't super dense, you still need to consider gate count and don't waste resources. Efficient state machines, appropriate data path widths, and avoiding unnecessary logic matter.

Timing Constraints: The process isn't extremely fast. Expect clock frequencies in the tens to hundreds of MHz range for typical designs (not GHz like advanced nodes). Understanding this helps you set realistic timing goals.

Power Awareness: While not as power-efficient as modern processes, 130nm is decent for low-power designs with proper techniques (clock gating, power domains, voltage scaling).

I/O Flexibility: The multi-voltage I/O capability means you can interface with various standards and legacy systems easily.

Mixed-Signal Opportunities: The process's analog capabilities enable designs combining digital processing with sensor interfaces, data converters, or RF communication—true system-on-chip designs.

Conclusion: Empowerment Through Openness

The Skywater 130nm PDK represents more than just technical data—it's a democratization of chip design. For decades, semiconductor technology was locked behind walls of NDAs and access fees, creating an elite club of those who could participate. The open PDK movement, pioneered by Skywater and Google, tears down these walls.

Understanding what a PDK is—the comprehensive collection of design rules, standard cells, models, and documentation—helps you appreciate the complexity of real chip design while recognizing that it's now accessible to anyone willing to learn. The 130nm node, despite its "old" status in an industry obsessed with the latest nanometer, provides a mature, capable platform for learning and for building real products.

The distinction between technology node names and actual feature sizes reminds us to look beyond marketing at the underlying physics and engineering. "130nm" doesn't mean everything is 130 nanometers, but it does indicate a certain level of capability, density, and manufacturing maturity.

As we move forward in this course, you'll see how Yosys synthesizes your RTL using the Skywater standard cells, how place-and-route tools arrange these cells according to the design rules, and how your abstract hardware description transforms into a physical layout ready for fabrication. The PDK is the Rosetta Stone that makes this translation possible.

In the next section, we'll dive into installing and configuring the Skywater PDK, exploring its structure, and understanding how to reference it from synthesis tools. The journey from abstract logic to physical silicon begins with understanding this crucial layer of the design flow.