Analyzing Synthesis Results

From Numbers to Insights: Reading What Synthesis Tells You

You've successfully synthesized your design—RTL transformed into gates, mapped to your technology library, and optimized according to your constraints. Now comes a critical skill that separates novice designers from experts: analyzing the results. A synthesis tool can produce a netlist, but only you can determine if that netlist is good, identify problems before they become expensive mistakes, and understand the trade-offs being made.

Synthesis produces vast amounts of data: gate counts, area estimates, timing reports, and structural netlists. Learning to extract insights from this data enables you to iterate intelligently, optimize effectively, and catch issues early. This module teaches you to read synthesis reports like a professional, visualize netlists to understand structure, and compare results across different corners and optimizations.

Gate Count and Area Reports: The stat Command

Understanding stat Output

The stat command is your primary tool for understanding synthesis results at a high level:

Basic Usage

yosys> stat

Sample Output

=== design hierarchy ===

   top                                  1
   
=== counter ===

   Number of wires:                 45
   Number of wire bits:            109
   Number of public wires:          13
   Number of public wire bits:      37
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 32
     AND2_X1                         6
     DFF_X1                          8
     INV_X1                         12
     NAND2_X1                        4
     OR2_X1                          2

Interpreting Wire Statistics

Number of wires: Total internal signals in the design

• Includes both visible ports and internal connections
• Higher numbers indicate more complex connectivity

Number of wire bits: Total bit-width across all wires

• An 8-bit bus counts as 8 wire bits
• Useful for understanding data-path complexity

Public wires: Module ports and named signals

• Signals that appear in the module interface
• Important for hierarchy and testbench connection

Example Analysis

Number of wires: 45
Number of wire bits: 109

This suggests:

• 45 distinct signals/connections
• Average width of ~2.4 bits per signal
• Mix of control signals (1-bit) and data paths (multi-bit)

Interpreting Cell Statistics

Cell Breakdown by Type

Number of cells:                 32
  AND2_X1                         6
  DFF_X1                          8
  INV_X1                         12
  NAND2_X1                        4
  OR2_X1                          2

Key Metrics:

• Total cell count: 32 gates (area proportional to this)
• Sequential cells: 8 flip-flops (register count)
• Combinational cells: 24 gates (logic complexity)
• Ratio: 25% sequential, 75% combinational (typical for data-path logic)

Cell Type Analysis:

• INV_X1: 12 inverters (37.5% of combinational logic)
  • High inverter count might indicate suboptimal logic structure
  • Or could be appropriate for heavy inversion-based design
• AND2_X1: 6 gates (18.75%)
• NAND2_X1: 4 gates (12.5%)
• OR2_X1: 2 gates (6.25%)

Area Reporting with Liberty

Enhanced Statistics with Library Data

yosys> stat -liberty

Sample Output

=== counter ===

   Number of cells:                 32
     AND2_X1                         6
     DFF_X1                          8
     INV_X1                         12
     NAND2_X1                        4
     OR2_X1                          2

Chip area for module '\counter': 89.456

Understanding Area Numbers:

• Units: Defined in Liberty file (typically μm² or "library units")
• Components: Sum of all cell areas
• Interpretation: Larger area = higher cost, potentially more power

Detailed Area Breakdown

yosys> stat -liberty -width

Adds bit-width information for data-path analysis.

Comparing Different Optimizations

Area-Focused Synthesis

yosys> abc -liberty cells.lib -fast
yosys> stat -liberty
Chip area: 89.456

Timing-Focused Synthesis

yosys> abc -liberty cells.lib -D 1500
yosys> stat -liberty
Chip area: 127.832  (43% increase for timing)

Interpretation: Achieving faster timing required:

• Larger drive strengths (X2, X4 instead of X1)
• Additional buffering
• 43% area penalty

This quantifies the area-timing trade-off.

Cell Distribution Analysis

Understanding Your Logic Mix

Sequential:  8/32  = 25%  (DFF_X1)
Inverters:  12/32  = 37.5% (INV_X1)
Logic:      12/32  = 37.5% (AND, NAND, OR)

Typical Patterns:

• Control logic: 10-30% sequential, high inverter ratio
• Data-path: 5-15% sequential, lower inverter ratio, more complex gates
• State machines: 30-50% sequential, moderate combinational logic

Red Flags:

• Very high inverter ratio (>50%): Might indicate poor synthesis or unusual RTL
• Very low sequential ratio (<5%) in supposedly sequential design: Check for unintended combinational inference
• Excessive buffer count: Might indicate load/fanout problems

Critical Path Identification

Understanding Critical Paths

The critical path is the longest delay path through your design—it determines maximum operating frequency.

Path Components

Launch FF → Combinational Logic → Capture FF

The critical path delay includes:

1. Clock-to-Q delay of launch flip-flop
2. Propagation through combinational gates
3. Setup time of capture flip-flop

Yosys Timing Analysis Limitations

Important Note: Yosys performs limited timing analysis. For production timing closure, use:

• OpenSTA (Static Timing Analyzer)
• Commercial STA tools (PrimeTime, Tempus)

Yosys can provide:

• Estimated delays from ABC
• Structural path identification
• Relative timing comparisons

Identifying Long Paths in Yosys

Method 1: ABC Timing Reports

ABC provides delay estimates during mapping:

yosys> abc -liberty cells.lib -D 2000

ABC reports:

• Target delay: 2000ps
• Actual achieved: 1850ps
• Slack: 150ps (positive = timing met)

Method 2: Manual Path Tracing

# Find long combinational paths
yosys> select -module counter t:$logic
yosys> show -prefix logic_paths

Visual inspection of the netlist can reveal:

• Long chains of gates
• High-fanout nets
• Complex logic trees

Method 3: Statistical Analysis

yosys> stat -liberty

Compare area across optimizations:

• Higher area often correlates with faster paths (larger drive strengths)
• Dramatic area increase indicates aggressive timing optimization

Critical Path Characteristics

Common Critical Path Sources:

1. Arithmetic Operations

   • Adders, multipliers (especially ripple-carry structures)
   • Long carry chains

2. Multiplexer Trees

   • Wide multiplexers (64:1, 128:1)
   • Cascaded multiplexers

3. Complex Boolean Logic

   • Deep logic cones
   • High-fanin gates

4. Long Interconnect

   • Signals crossing large distances
   • High-capacitance nets

Example: Identifying Adder as Critical Path

yosys> stat

Number of cells:
  ADDF_X1       8    # 8-bit adder
  DFF_X1       16    # Input and output registers
  # Other logic...

Chip area: 234.5

The 8 full adders form a carry chain—likely the critical path. Solutions:

• Use carry-lookahead adder
• Pipeline the adder (break into stages)
• Reduce bit-width if possible

Netlist Visualization: The show Command

Basic Visualization

Generate Schematic

yosys> show

This opens a graphical viewer showing:

• Cells as boxes
• Connections as lines
• Hierarchy as nested structures

Common Viewers:

• xdot (default, interactive)
• Web browser (for SVG output)
• Image viewer (for PNG output)

Controlling Visualization

Specify Output Format

yosys> show -format svg -prefix design

Generates design.svg file viewable in any browser.

Format Options:

• dot: GraphViz DOT format (text)
• svg: Scalable Vector Graphics (web-friendly)
• ps: PostScript (print-quality)
• png: Raster image (for documents)

Size Control

yosys> show -width

Includes bit-widths on connections (useful for data-path analysis).

Viewing Specific Modules

yosys> show counter

Shows only the specified module (useful for large hierarchical designs).

Interpreting Schematics

Standard Representation:

┌─────────┐
│ Cell    │
│ Type    │
│ Name    │
└─────────┘

Example Schematic Elements:

      ┌────────┐
─A───▶│        │
      │ AND2_X1│────Y───▶
─B───▶│   u1   │
      └────────┘

      ┌────────┐
─D───▶│        │────Q───▶
      │ DFF_X1 │
clk──▶│   ff1  │
      └────────┘

Visual Cues:

• Wide connections: Multi-bit buses (shown as thick lines)
• Fanout points: One signal driving multiple inputs (branching)
• Feedback loops: Combinational cycles (error!) or intentional feedback

Using Visualization for Debugging

Scenario 1: Unexpected Cell Count

You expect ~20 gates but see 200:

yosys> show

Visual inspection reveals:

• Large fanout tree (1 signal driving 100 flip-flops)
• Automatic buffer insertion by ABC
• Solution: Add buffering in RTL or adjust ABC strategy

Scenario 2: Combinational Loop

Synthesis warns about loops:

Warning: Found combinational loop

yosys> show

Visual shows:

• Signal feeding back to itself
• Typically a latch inference issue
• Fix: Add clock edge or default case in RTL

Scenario 3: Inefficient Structure

yosys> show

You see:

• Long chain of inverters (should be reduced)
• Redundant logic (should be optimized away)
• Indicates optimization passes didn't run or RTL issue

Advanced Visualization

Filter Display

yosys> select t:DFF_X1
yosys> show -color red

Highlights all flip-flops in red (useful for analyzing register placement).

Hierarchy Visualization

yosys> show -prefix hier -format svg

Shows module instantiation hierarchy (not gate-level detail).

Comparing Before/After

yosys> show -prefix before_opt
yosys> opt
yosys> show -prefix after_opt

Visual diff shows optimization impact.

Understanding the Synthesized Netlist

Netlist Structure

Verilog Netlist Format

module counter (
    input clk,
    input rst,
    output [7:0] count
);
  wire _0_;
  wire _1_;
  wire [7:0] _2_;
  wire [7:0] _3_;
  
  DFF_X1 _4_ (
    .D(_0_),
    .CK(clk),
    .Q(count[0])
  );
  
  INV_X1 _5_ (
    .A(count[0]),
    .Y(_1_)
  );
  
  // More instances...
endmodule

Reading Netlist Elements

Wire Declarations

wire _0_;        // Internal signal
wire [7:0] _2_;  // 8-bit internal bus

Anonymous wires (_0_, _1_) are synthesis-generated. Original names lost during optimization unless preserved.

Cell Instantiations

DFF_X1 _4_ (
  .D(_0_),
  .CK(clk),
  .Q(count[0])
);

• DFF_X1: Cell type from library
• _4_: Instance name (synthesis-generated)
• .D(...): Port connections

Preserving Signal Names

Default Behavior: Optimization removes signal names

// Original RTL
wire [7:0] sum;

// Netlist
wire [7:0] _42_;  // sum is lost

Preserving Names

yosys> write_verilog -noattr -noexpr design.v

Still generates anonymous names but preserves structure.

Better Preservation Use attributes in RTL:

(* keep *) wire [7:0] sum;

Yosys preserves nets marked with keep attribute.

Tracing Through the Netlist

Manual Path Tracing

Find a signal path:

1. Start at input or register output
2. Find gate driven by that signal
3. Trace to gate output
4. Follow output to next gate input
5. Repeat until reaching register or output

Example:

Input 'enable' →
  INV_X1 _10_ (inverts enable) →
  AND2_X1 _11_ (ANDs with count[0]) →
  ADDF_X1 _12_ (adds to counter) →
  DFF_X1 _13_ (stores result) →
  Output 'count[0]'

Common Netlist Patterns

Pattern 1: Counter

DFF → Adder → Mux (enable) → DFF
         ↑              ↓
         └──────────────┘

Pattern 2: State Machine

DFF (state) → Decoder → Next State Logic → Mux → DFF (state)
            ↓
         Output Logic

Pattern 3: Data Path

DFF (A) ──┐
          ├→ Adder/ALU → Mux → DFF (Result)
DFF (B) ──┘              ↑
                         │
                    Control Logic

Recognizing these patterns helps understand design structure.

Comparing Synthesis Results Across Corners

Why Compare Corners?

Different corners produce different implementations:

• SS corner: Larger cells to meet timing (high area)
• TT corner: Balanced implementation (medium area)
• FF corner: Smaller cells acceptable (low area)

Comparing reveals:

• How much timing margin exists
• Whether corner-specific optimizations are effective
• If hold timing might be problematic (FF corner)

Setting Up Comparison

Synthesize All Corners

$ yosys -s synthesis_ss.ys > synth_ss.log
$ yosys -s synthesis_tt.ys > synth_tt.log
$ yosys -s synthesis_ff.ys > synth_ff.log

Extract Statistics

$ grep "Chip area" synth_ss.log > area_ss.txt
$ grep "Chip area" synth_tt.log > area_tt.txt
$ grep "Chip area" synth_ff.log > area_ff.txt

Comparative Analysis

Area Comparison

Corner   Area (μm²)   Cells   Cell Density
SS       145.6        38      3.83 μm²/cell
TT       124.3        35      3.55 μm²/cell
FF       118.7        34      3.49 μm²/cell

Interpretation:

• SS corner 23% larger than FF (expected due to upsizing)
• Cell count varies slightly (38 vs 34)
• Average cell size increases in SS corner (larger drive strengths)

Cell Type Comparison

Cell Type     SS    TT    FF
DFF_X1         8     8     8   (same - sequential count fixed)
INV_X1         8    10    12   (fewer in SS, more powerful)
INV_X2         4     2     0   (SS needs higher drive)
INV_X4         2     0     0   (SS only)
AND2_X1        5     6     7   (more small cells in FF)
AND2_X2        3     2     1   (SS upsizes for timing)

Key Observations:

• Sequential cells identical (register count independent of corner)
• SS corner shifts toward higher drive strengths (X2, X4)
• FF corner uses more X1 cells (sufficient speed at fast corner)

Normalized Comparison

Calculate Relative Metrics

Metric           SS       TT      FF      SS/TT    FF/TT
Area (μm²)      145.6   124.3   118.7    +17%     -4.5%
Cell count        38      35      34      +8.6%    -2.9%
Avg cell area    3.83    3.55    3.49    +7.9%    -1.7%

Normalized to TT Corner:

• SS corner: 17% more area (timing-driven upsizing)
• FF corner: 4.5% less area (can use smaller cells)

Visual Comparison

Generate Schematics

yosys> show -prefix netlist_ss -format svg
yosys> show -prefix netlist_tt -format svg
yosys> show -prefix netlist_ff -format svg

Side-by-Side Comparison: Visual inspection shows:

• Same overall structure (topology identical)
• Different cell types at specific locations
• Drive strength variations highlighted

Difference Analysis Tool (manual)

$ diff netlist_tt.v netlist_ss.v

Shows which cells changed between corners.

Timing Margin Analysis

Estimating Margin

If ABC reported delays:

Corner   Target (ps)   Achieved (ps)   Slack (ps)   Margin
SS       2000          1850            150          7.5%
TT       1800          1620            180          10%
FF       1600          1380            220          13.8%

Interpretation:

• All corners meet timing (positive slack)
• FF corner has most margin (13.8%)
• SS corner has least margin (7.5%) - might need attention if critical
• TT corner balanced

Hold Time Considerations

FF Corner Focus

Fast corner has shortest delays:

• Risk: Hold time violations
• Signals propagate too fast between registers
• Data changes before capture flip-flop's hold time satisfied

Checking for Hold Issues:

yosys> stat -liberty
# Look for minimum delay paths

If FF corner has very low cell counts and small drive strengths:

• Hold violations possible
• May need minimum delay constraints
• Post-synthesis STA (OpenSTA) essential

Practical Comparison Workflow

Automated Comparison Script

#!/bin/bash
# compare_corners.sh

echo "Corner Comparison Report"
echo "========================"

for corner in ss tt ff; do
    echo ""
    echo "Corner: $corner"
    grep "Chip area" output/${corner}/stats.txt
    grep "Number of cells:" output/${corner}/stats.txt
done

echo ""
echo "Relative to TT:"
# Calculate percentages...

Integration with Regression

compare: synth_all
	./compare_corners.sh > reports/corner_comparison.txt
	@cat reports/corner_comparison.txt

Practical Analysis Example

Complete Analysis Workflow

Design: 8-bit ALU

Step 1: Synthesize All Corners

$ make synth_all

Step 2: Collect Statistics

$ yosys -s analyze.ys

analyze.ys

# Load each corner result
foreach corner {ss tt ff} {
    design -reset
    read_verilog output/${corner}/alu_mapped.v
    
    stat -liberty
    tee -o reports/stats_${corner}.txt stat
    
    # Generate schematic
    show -prefix reports/alu_${corner} -format svg
}

Step 3: Compare Results

Corner   Area    Cells   Sequential   Combinational
SS       234.5    67        16            51
TT       198.3    62        16            46
FF       189.7    60        16            44

Step 4: Identify Issues

• SS corner 24% larger than TT (high area penalty)
• Might benefit from relaxed timing constraint
• Sequential count correct (16 registers expected)

Step 5: Optimize

# Relax SS corner constraint slightly
abc -liberty cells_ss.lib -D 2200  # was 2000

# Re-run
stat -liberty
# New area: 210.4 (10% reduction, still meets timing)

Step 6: Document

Final Results:
- SS corner optimized: 210.4 μm² (meets 2.2ns)
- TT corner: 198.3 μm² (meets 2.0ns)
- FF corner: 189.7 μm² (meets 1.8ns)
- Area variation: 11% (acceptable)

Summary

Analyzing synthesis results transforms raw data into actionable insights:

• stat command provides gate counts, area metrics, and cell type breakdowns
• Critical path identification reveals timing bottlenecks and optimization opportunities
• Netlist visualization with show enables structural understanding and debugging
• Understanding netlists requires tracing paths and recognizing patterns
• Cross-corner comparison validates robustness and reveals optimization trade-offs

Key skills you've developed:

• Reading and interpreting stat output
• Identifying critical paths and timing issues
• Using visualization for debugging and understanding
• Tracing through synthesized netlists
• Comparing results across multiple corners
• Making data-driven optimization decisions

With these analysis skills, you can confidently evaluate synthesis results, identify areas for improvement, and iterate toward optimal designs. You're no longer blindly accepting what the tool produces—you understand what the numbers mean, can spot problems early, and know how to optimize intelligently.

In the next modules, we'll integrate these synthesis results with static timing analysis, perform power analysis, and prepare designs for physical implementation. The foundation you've built in synthesis and analysis will serve you throughout the entire design flow.