Quick Reference Cheat Sheet

Introduction to Quick References

This appendix provides condensed command references for the primary open-source EDA tools used throughout this course. These cheatsheets are designed for quick lookup during development and serve as reminders of syntax and options once you understand the underlying concepts.

Organization: Each section covers one tool with commands grouped by function. Common use cases are highlighted with examples.

Usage Tips:

• Bookmark this page for quick access during projects
• Use Ctrl+F to search for specific commands or options
• Examples use design.v as a placeholder—replace with your actual filenames
• Options in [brackets] are optional; options in <angles> are required

1. Icarus Verilog Command Cheatsheet

Icarus Verilog (iverilog) is an open-source Verilog compiler and simulator. It compiles Verilog source into an executable simulation.

Basic Compilation and Simulation

# Simple compile and simulate
iverilog -o simv design.v testbench.v
vvp simv

# With waveform dump (VCD)
iverilog -o simv design.v testbench.v
vvp simv
# VCD file generated by $dumpfile/$dumpvars in testbench

# View waveforms
gtkwave waveform.vcd

Compilation Options

Advanced Compilation

# Multiple source files
iverilog -o simv file1.v file2.v file3.v testbench.v

# Using file list
iverilog -o simv -f filelist.f
# filelist.f contains:
#   rtl/alu.v
#   rtl/decoder.v
#   tb/testbench.v

# With include paths and defines
iverilog -o simv \
  -Iinclude/ \
  -DSIM -DDEBUG \
  -g2012 \
  -Wall \
  design.sv testbench.sv

# Specify target (for synthesis info)
iverilog -tvlog95 -o netlist.v design.v  # Output Verilog-95

Simulation (vvp) Options

Common Simulation Commands

# Run with timeout
vvp simv +timeout=10000

# Multiple VCD files (specified in testbench)
vvp simv +vcdfile=wave.vcd

# Verbose simulation
vvp -v simv

# Redirect output
vvp simv > simulation.log 2>&1

Preprocessor Macros in Testbench

// Access compile-time defines
`ifdef SIM
  initial $display("Running in simulation mode");
`endif

`ifdef DEBUG
  initial $monitor("time=%0t data=%h", $time, data);
`endif

// Use plusargs at runtime
initial begin
  if ($test$plusargs("debug"))
    $display("Debug mode enabled");
end

Quick Workflow Example

# Complete simulation workflow
# 1. Compile
iverilog -g2012 -Wall \
  -DSIM -DWIDTH=32 \
  -Iinclude/ \
  -o simv \
  rtl/design.sv \
  testbench/tb.sv

# 2. Simulate
vvp simv -lsim.log +timeout=50000

# 3. View waveforms
gtkwave dump.vcd &

# 4. Check results
grep -i "error\|fail" sim.log

2. Verilator Lint Warning Reference

Verilator is a fast open-source Verilog/SystemVerilog simulator and linter. Its lint mode catches common RTL issues.

Running Lint

# Basic lint check
verilator --lint-only design.v

# With all warnings
verilator --lint-only -Wall design.v

# Specific top module
verilator --lint-only --top-module my_design design.v

# Multiple files
verilator --lint-only file1.v file2.v

# With include paths
verilator --lint-only -Iinclude/ design.v

# Suppress specific warnings
verilator --lint-only -Wno-UNUSED design.v

Common Warning Categories

Critical Warnings (Always Fix)

Style Warnings (Should Fix)

Informational (Context-Dependent)

Detailed Warning Examples

BLKSEQ - Blocking in Sequential

// BAD - generates BLKSEQ warning
always @(posedge clk) begin
  a = b + 1;  // Wrong: blocking in sequential
  c = a + 1;
end

// GOOD - no warning
always @(posedge clk) begin
  a <= b + 1;  // Correct: non-blocking
  c <= a + 1;
end

LATCH - Inferred Latch

// BAD - generates LATCH warning
always @(*) begin
  if (enable)
    out = in;
  // Missing else: out keeps old value = latch!
end

// GOOD - no warning
always @(*) begin
  if (enable)
    out = in;
  else
    out = 1'b0;  // All paths covered
end

WIDTH - Width Mismatch

// BAD - generates WIDTH warning
wire [7:0] a;
wire [15:0] b;
assign b = a;  // Implicit zero-extension

// GOOD - explicit width handling
wire [7:0] a;
wire [15:0] b;
assign b = {8'b0, a};  // Explicit zero-extension

UNUSED - Unused Signal

// BAD - generates UNUSED warning
module example(input clk, input data, output result);
  wire intermediate;  // Declared but never used
  assign result = data;
endmodule

// GOOD - remove unused signal
module example(input clk, input data, output result);
  assign result = data;
endmodule

Suppressing Warnings

// Suppress specific warning for one line
/* verilator lint_off UNUSED */
wire debug_signal;
/* verilator lint_on UNUSED */

// Suppress for entire module
/* verilator lint_off WIDTH */
module my_design (...);
  // Width mismatches allowed here
endmodule
/* verilator lint_on WIDTH */

// Suppress specific instance
wire [3:0] small;
wire [7:0] large;
/* verilator lint_off WIDTH */
assign large = small;
/* verilator lint_on WIDTH */

Lint Configuration File

# Create .verilator_lint_config
# Suppress globally
lint_off -rule UNUSED
lint_off -rule DECLFILENAME

# Run with config
verilator --lint-only -f .verilator_lint_config design.v

3. Yosys Command Reference

Yosys is an open-source synthesis framework for RTL-to-gate conversion.

Basic Yosys Workflow

# Interactive mode
yosys

# Script mode
yosys -s synthesis_script.ys

# One-liner
yosys -p "read_verilog design.v; synth; write_verilog synth.v"

Essential Commands by Category

Reading Design Files

# Read Verilog
read_verilog design.v
read_verilog -sv design.sv  # SystemVerilog

# Read multiple files
read_verilog file1.v file2.v

# Read with defines
read_verilog -D WIDTH=32 -D SYNTHESIS design.v

# Read BLIF
read_blif design.blif

# Read JSON (Yosys format)
read_json design.json

# Set hierarchy
hierarchy -check              # Check hierarchy
hierarchy -top my_design      # Set top module
hierarchy -auto-top           # Auto-detect top

Synthesis Passes

# High-level synthesis (recommended)
synth                    # Generic synthesis
synth -top my_design     # Specify top module
synth -auto-top          # Auto-detect top

# Target-specific synthesis
synth_ice40             # iCE40 FPGA
synth_ecp5              # ECP5 FPGA
synth_xilinx            # Xilinx FPGA
synth_intel             # Intel FPGA

# Manual pass sequence
proc                    # Process Verilog processes
opt                     # Optimization
fsm                     # FSM extraction/optimization
opt                     # Optimization again
memory                  # Memory mapping
opt                     # More optimization
techmap                 # Technology mapping
opt                     # Final optimization

Technology Mapping

# Map to Liberty library
abc -liberty lib/mycells.lib

# Map with timing constraints
abc -liberty lib/mycells.lib -constr constraints.sdc

# Show ABC script
abc -script +strash;scorr;ifraig;retime;dch,-f;map,-M,1

# Cell library setup
read_liberty -lib lib/mycells.lib
dfflibmap -liberty lib/mycells.lib
abc -liberty lib/mycells.lib

Optimization Commands

opt                    # General optimization
opt_expr               # Constant folding, expression optimization
opt_clean              # Remove unused signals
opt_reduce             # Reduce operator widths
opt_merge              # Merge identical cells
opt_muxtree            # Optimize multiplexer trees
opt_clean -purge       # Aggressive cleanup

# Specific optimizations
wreduce                # Reduce word sizes
peepopt                # Peephole optimization
muxcover               # Cover logic with muxes

Analysis and Reporting

# Statistics
stat                           # Basic statistics
stat -top my_design            # Stats for specific module
stat -liberty lib/cells.lib    # Stats with cell areas

# Show design
show                           # Display schematic (requires xdot)
show -prefix design -format svg  # Save as SVG

# Check design
check                          # Check for errors
hierarchy -check               # Check hierarchy

# List objects
ls                            # List modules
cd my_design                  # Change to module
ls -wires                     # List wires
ls -cells                     # List cells

# Print statistics
tee -o stats.txt stat         # Save stats to file

Writing Output

# Write Verilog netlist
write_verilog output.v
write_verilog -noattr output.v      # No attributes
write_verilog -noexpr output.v      # No expressions
write_verilog -norename output.v    # Keep original names

# Write BLIF
write_blif output.blif

# Write JSON
write_json output.json

# Write EDIF
write_edif output.edif

# Write for specific tool
write_verilog -defparam output.v    # Use defparam
write_verilog -v output.v            # Verilog-2001

Complete Synthesis Script Example

# synthesis.ys - Complete synthesis script

# Read design
read_verilog -sv rtl/design.sv
read_verilog -sv rtl/submodule.sv

# Hierarchy
hierarchy -check -top my_design

# High-level synthesis
proc; opt; fsm; opt; memory; opt

# Technology mapping
read_liberty -lib lib/mycells.lib
dfflibmap -liberty lib/mycells.lib
abc -liberty lib/mycells.lib
opt_clean -purge

# Statistics
tee -o reports/stats.txt stat -liberty lib/mycells.lib

# Write outputs
write_verilog -noattr output/synthesized.v
write_json output/design.json

# Visualize (optional)
show -prefix output/schematic -format svg

Command-Line Usage

# Run script
yosys -s synthesis.ys

# One-line synthesis
yosys -p "read_verilog design.v; synth; write_verilog out.v"

# With logging
yosys -s synthesis.ys -l synthesis.log

# Quiet mode
yosys -q -s synthesis.ys

# Define macros
yosys -p "read_verilog -D SIM design.v; synth"

4. OpenSTA / SDC Command Reference

OpenSTA is an open-source static timing analysis tool using SDC (Synopsys Design Constraints) format.

Running OpenSTA

# Interactive mode
sta

# Script mode
sta -f timing_analysis.tcl

# Non-interactive
sta -exit timing_analysis.tcl

Essential SDC Commands

Clock Definition

# Create clock
create_clock -period <period> -name <name> [get_ports <port>]
create_clock -period 10.0 -name clk [get_ports clk]

# Create generated clock
create_generated_clock -name clk_div2 \
  -source [get_ports clk] \
  -divide_by 2 \
  [get_pins divider/Q]

# Virtual clock (for I/O timing)
create_clock -period 10.0 -name virtual_clk

# Clock groups (for CDC)
set_clock_groups -asynchronous \
  -group [get_clocks clk_a] \
  -group [get_clocks clk_b]

# Clock uncertainty (jitter/skew)
set_clock_uncertainty -setup 0.5 [get_clocks clk]
set_clock_uncertainty -hold 0.3 [get_clocks clk]

# Clock latency
set_clock_latency -source 1.0 [get_clocks clk]  # Source latency
set_clock_latency 0.5 [get_clocks clk]          # Network latency

# Clock transition
set_clock_transition 0.2 [get_clocks clk]

Input/Output Delays

# Input delays
set_input_delay -clock <clk> -max <delay> [get_ports <port>]
set_input_delay -clock clk -max 2.0 [get_ports data_in]
set_input_delay -clock clk -min 0.5 [get_ports data_in]

# Input delay for all inputs
set_input_delay -clock clk -max 2.0 [all_inputs]

# Output delays
set_output_delay -clock clk -max 1.5 [get_ports data_out]
set_output_delay -clock clk -min -0.5 [get_ports data_out]

# Output delay for all outputs
set_output_delay -clock clk -max 1.5 [all_outputs]

Environmental Constraints

# Input drive strength
set_driving_cell -lib_cell INV_X4 [get_ports data_in]
set_driving_cell -lib_cell BUF_X8 [all_inputs]

# Input transition time (alternative to driving cell)
set_input_transition 0.3 [get_ports data_in]

# Output load
set_load -pin_load 0.05 [get_ports data_out]
set_load -wire_load 0.02 [all_outputs]

# Fanout limit
set_max_fanout 16 [current_design]
set_max_fanout 8 [get_ports enable]

# Transition limits
set_max_transition 1.0 [current_design]

# Capacitance limits
set_max_capacitance 0.5 [current_design]

Timing Exceptions

# False path (path not used functionally)
set_false_path -from [get_ports reset] -to [all_registers]
set_false_path -through [get_pins mux/SEL]

# Multi-cycle path
set_multicycle_path -setup 2 \
  -from [get_pins reg1/Q] \
  -to [get_pins reg2/D]
set_multicycle_path -hold 1 \
  -from [get_pins reg1/Q] \
  -to [get_pins reg2/D]

# Max delay constraint
set_max_delay 5.0 -from [get_ports in] -to [get_ports out]

# Min delay constraint
set_min_delay 0.5 -from [get_ports in] -to [get_ports out]

Case Analysis

# Fix signal value for timing analysis
set_case_analysis 0 [get_ports test_mode]
set_case_analysis 1 [get_ports scan_enable]

OpenSTA-Specific Commands

Reading Design

# Read Liberty library
read_liberty lib/mycells.lib
read_liberty -min lib/mycells_fast.lib
read_liberty -max lib/mycells_slow.lib

# Read Verilog netlist
read_verilog netlist.v

# Link design
link_design my_design

# Read parasitics (SPEF/SDF)
read_spef design.spef
read_sdf design.sdf

# Read SDC constraints
read_sdc constraints.sdc

Timing Analysis

# Report timing
report_checks
report_checks -path_delay max        # Setup checks
report_checks -path_delay min        # Hold checks
report_checks -path_delay max_rise   # Max rising
report_checks -path_delay max_fall   # Max falling

# Detailed timing report
report_checks -format full_clock_expanded
report_checks -fields {slew cap input nets fanout}

# Report specific paths
report_checks -from [get_ports in] -to [get_ports out]
report_checks -through [get_pins alu/carry]

# Report multiple paths
report_checks -path_delay max -max_paths 10

# Report all violating paths
report_checks -path_delay max -slack_max 0.0

# Worst slack
report_worst_slack
report_worst_slack -max              # Setup
report_worst_slack -min              # Hold

# Slack histogram
report_checks -slack_max 0 -format summary

# Total negative slack
report_tns

Design Queries

# Get objects
get_ports *                          # All ports
get_ports data*                      # Pattern match
get_pins cell/Q                      # Specific pin
get_nets net1                        # Net
get_cells *                          # All cells
get_clocks *                         # All clocks
get_libs *                           # All libraries

# Filters
all_inputs                           # All input ports
all_outputs                          # All output ports
all_registers                        # All flip-flops
all_clocks                           # All clocks

# Querying properties
get_property [get_pins ff/Q] max_transition

Reporting

# Clock report
report_clocks

# Design statistics
report_design

# Liberty library info
report_lib

# Pin information
report_pin [get_pins cell/Q]

# Annotated delays
report_annotated_delay -list_not_annotated

Complete Timing Analysis Script

# timing_analysis.tcl

# Read libraries (multi-corner)
read_liberty -min lib/mycells_fast.lib
read_liberty -max lib/mycells_slow.lib

# Read design
read_verilog netlist/design.v
link_design my_design

# Read parasitics
read_spef parasitic/design.spef

# Read constraints
read_sdc constraints/design.sdc

# Setup analysis
puts "Setup Analysis"
report_checks -path_delay max -max_paths 100 \
  > reports/setup_timing.rpt

# Hold analysis  
puts "Hold Analysis"
report_checks -path_delay min -max_paths 100 \
  > reports/hold_timing.rpt

# Worst slack
report_worst_slack -max > reports/worst_slack.rpt
report_worst_slack -min >> reports/worst_slack.rpt

# Summary
puts "\n=== Timing Summary ==="
report_checks -format summary

# Exit
exit

Running Example

# Complete timing analysis flow
sta -exit timing_analysis.tcl > timing.log

# Check for violations
grep -i "slack" timing.log
grep -i "VIOLATED" timing.log

# Quick check
sta -exit -c "
  read_liberty lib.lib;
  read_verilog design.v;
  link_design top;
  read_sdc design.sdc;
  report_checks
"

Using These References

Tips for Effective Use:

1. Start Simple: Use basic commands first, add complexity as needed
2. Check Examples: Each tool section includes working examples
3. Combine Tools: Use Icarus for simulation, Verilator for lint, Yosys for synthesis, OpenSTA for timing
4. Keep Updated: Tool versions evolve; check --help for latest options
5. Script Everything: Automate with Makefiles or shell scripts

Typical Design Flow:

# 1. Lint check
verilator --lint-only -Wall design.v

# 2. Simulate
iverilog -o simv -g2012 design.v tb.v
vvp simv

# 3. Synthesize
yosys -s synthesis.ys

# 4. Timing analysis
sta -f timing.tcl

These quick references serve as your desktop companion throughout the design process. Master the basics, then explore advanced options as your designs grow in complexity.

Additional Resources:

• Icarus Verilog: http://iverilog.icarus.com/
• Verilator: https://verilator.org/
• Yosys: http://www.clifford.at/yosys/
• OpenSTA: https://github.com/The-OpenROAD-Project/OpenSTA