You've now taken one design through the entire ChipVerify Lab flow — from a blank project to a physically place-and-routed layout. Here's a quick recap, and where to go next.
4 min read | Beginner Level
What You'll Learn
- A recap of everything covered across the series
- A consolidated view of what's FREE and what's PRO
- Where to explore next inside ChipVerify Lab
Recap of the Full Flow
| Chapter | What You Did |
|---|---|
| 1. Your First Project | Wrote a 4-bit universal shift register with real hierarchy |
| 2. Simulate & Verify | Ran a testbench and read the waveform |
| 3. Lint & Synthesize | Cleaned up a lint warning and synthesized to gates |
| 4. Explore the Schematic | Read the schematic and navigated into hierarchy |
| 5. Analyze PPA & Timing | Read area/power and ran full timing analysis |
| 6. Synthesizing Across Libraries | Compared PPA across standard-cell libraries |
| 7. Physical Design | Ran place-and-route and reviewed design rule checking |
| 8. Ask AI | Debugged a run with the built-in assistant |
| 9. Coverage Reports | Measured and closed a verification coverage gap |
| 10. Learning Sessions | Tracked runs, diffs, and notes across a session |
Where FREE Stops and PRO Starts
| Feature | FREE | PRO |
|---|---|---|
| Simulation (Icarus & Verilator) | Yes | Yes |
| Lint & basic synthesis | Yes | Yes |
| Synthesis libraries/corners | ms / typical only | All 5 libraries, all 3 corners |
| Full STA | No | Yes |
| PPA History comparison | No | Yes |
| Place & Route | Yes (capped, fixed flow) | Yes (uncapped, custom TCL) |
| DRC | No | Yes |
| Ask AI | Yes (your own API key) | Yes (20 queries/day, no key needed) |
| Learning Sessions | No | Yes |
Explore Further
From here, the Examples library has more ready-to-run designs across Verilog, SystemVerilog, and UVM. The Challenges section scores your synthesis results against real PPA targets, and the Exercises section works through language and verification concepts one at a time with automated grading.
Ready to Upgrade?
If STA, additional libraries, DRC, or Learning Sessions would be useful for what you're working on next, the PRO plan covers all of them together.
Summary
In this series, you learned:
- The full ChipVerify Lab flow: design, verify, synthesize, analyze, and implement
- How to read and navigate a schematic, including its hierarchy
- How to compare PPA across libraries and iterate on timing constraints
- Where FREE stops and PRO starts, feature by feature
