Interview Question Bank

$stop is used to suspend the simulation at the point where it is called, simulator license is not released and still runs as a process in host operating system. User has to restart it, typically by manually resuming the simulation from the paused point.

$finish immediately terminates the simulation process and passes control back to the operating system, and license is released because simulation has exited.

$stop is useful for debugging and inspection of intermediate results in the design, allowing designers to examine signals, waveforms, or variables at a specific point in execution, while $finish is used at the end of the simulation, indicating that the design has completed its operation.

A frequency divider by 2 can be designed using a D flip-flop as follows:

    _________________
   |     ________    |
   |    |        |   |
   '--->|D     Q'|---'
        |        |
        |      Q |---- clk/2
        |___^____|
            |
 clk _______|    

The input clock signal Clk drives the clock input of the D flip-flop. The output of the flip-flop, Q, is connected back to the D input through an inverter to create a divide-by-2 circuit.

1. When the clock rises from low to high, the D flip-flop captures the value of the D input and outputs it on Q.
2. At the same time, the inverted output Q' feeds it back to the D input.
3. Thus, the output Q changes state on every positive edge of the clock, resulting in a frequency that is half of the input frequency.

Note that the input clock signal should have a duty cycle close to 50% to ensure reliable operation of the flip-flop. It is also important to ensure that the setup and hold times of the flip-flop are met to avoid timing errors.

$random is a system function that generates a new 32-bit random integer on every call with a seed value of 0 by default. The optional seed value is used to specify the starting point for the random number generator, and if specified, $random generates the same sequence of random numbers every time it is called with the same seed value. It has the following syntax:

$random(seed);

In Verilog, the default value of an uninitialized wire is 'z' or high-impedance and the default value of an uninitialized reg is 'x' or unknown. Read more on Verilog Data Types.

An intra-assignment delay is written between the = and the right-hand side. The right-hand side is evaluated immediately, and the assignment happens after the delay.

a = #5 b;   // b sampled now, a updated 5 time units later

An inter-assignment delay is written before the statement. Execution waits first, and the right-hand side is evaluated only after the delay.

#5 a = b;   // wait 5 time units, then sample b and update a

An event control such as @(posedge clk) in front of a statement works like an inter-assignment delay. A delay in a continuous assignment, assign #5 a = b;, is neither: it is an inertial delay on the net.

Read more on Verilog Inter and Intra Assignment Delay.

Infinite loops occur in programming when a loop does not have a condition to stop the iteration. Let's take a look at how infinite loops can get created in various looping constructs.

reg over;

initial begin
	over = 0;

	while (!over) begin
		#10 $display("[%0t] In Loop", $time);
	end
end

The while loop will only exit if some other process changes over to 1, and it will run forever if this does not happen.

Here is another example with for loop which will run forever because of a width mismatch in the looping variable. The looping variable i goes from 0 to 7, wraps back to 0, counts up again and never reach the exit loop condition.

reg [2:0] i;

initial begin

	for (i = 0; i < 16; i = i+1) begin
		$display("[%0t] i = %0d", $time, i);                       	
	end                       
end

If the range of the function return type is not specified, Verilog assumes it to be a 1 bit scalar value. There would not be any compilation errors but it will result in a functional error.

module tb;

	// Should have been function [3:0] add(input [31:0] a, b);
	// Returns 1 bit value by default
  	function add(input [3:0] a, b); 	
    	add = a + b;
  	endfunction

	initial begin
		$display("Sum = %0d", add(4, 5)); 	// Returns 1
	end
endmodule

Read more on Verilog Functions.

In Verilog, #0 is a delay specifier that represents zero time delay. It is processed after all active events at the current simulation time have been processed, and its usage is generally not recommended. Like all delays, it is not synthesizable either in designs.

module tb;
	reg [3:0] x;

	initial begin
      $monitor("[%0t] x = %0d", $time, x);

		x = 0;		
		#10 x = 10;
	end

	initial begin
		#10;
		#0 x = 15;   
	end	
endmodule

In the above code, the #0 delay will make the variable x get value 15 at the end of 10 time units.

To generate two different clocks in a testbench, you can use two different initial or always blocks to toggle the two clock signals. Here's an example Verilog code for generating two clock signals with different frequencies using initial blocks:

module tb;
  
  reg clk1;
  reg clk2;

  initial begin
    clk1 = 1'b0;
    forever #10 clk1 = ~clk1; // 50% duty cycle, period of 20 time units
  end

  initial begin
    clk2 = 1'b0;
    forever #5 clk2 = ~clk2; // 50% duty cycle, period of 10 time units
  end
  
  // Rest of the testbench code  
endmodule

In this code, two initial blocks are used to generate two clock signals, clk1 and clk2. The forever loops in each block toggle the clock signal at a specific frequency using the `#` delay operator. You can use these clock signals to drive different components in your design or to test the asynchronous behavior of your design.

A flip-flop can be implemented using a 2:1 MUX (multiplexer). Here's how you can implement a D flip-flop using a 2:1 MUX in Verilog:

module dff_using_mux(input d, clk, output q);
  wire out1;
  
  assign out1 = ~clk ? d  : out1;
  assign q    =  clk ? out1  : q;
  
endmodule

A modulo-3 counter has 3 states (0, 1, 2) and requires 2 flip-flops.

module cntr_mod3 (input clk, rstn, output reg [1:0] out);
  always @(posedge clk) begin
    if (!rstn)
      out <= 0;
    else 
      if (out == 2)
        out <= 0;
      else
      	out <= out + 1;
  end 
endmodule

In Verilog, you can override the existing parameter value in two ways:

1. In module instantiation

  module abc (input ..., output ...);
  	parameter RESET_VAL = 4;
  endmodule
  
  module xyz ();
  	abc #(.RESET_VAL (10)) u_abc ( ... );
  endmodule
  

2. Using defparam

  module abc (input ..., output ...);
  	parameter RESET_VAL = 4;
  endmodule
  
  module xyz ();
  	abc 	u_abc ( ... );
  
    defparam u_abc.RESET_VAL = 10;
  endmodule    
  

Read more on Verilog Parameters.

Synthesis is the process of converting a high-level hardware description language (HDL) code, such as Verilog or VHDL, into a gate-level netlist that can be used for physical implementation of a digital circuit on an integrated circuit (IC) or field-programmable gate array (FPGA).

The synthesis process involves analyzing the HDL code to determine the intended functionality of the circuit, optimizing the design for the desired performance and resource utilization, and generating a gate-level netlist that describes the circuit in terms of logic gates and flip-flops.

The synthesis tool analyzes the HDL code and performs a series of transformations to optimize the design. This can involve simplifying logic expressions, removing redundant logic, optimizing resource usage, and mapping the design to a specific target technology, such as an FPGA or ASIC. The synthesis tool then generates a gate-level netlist that can be processed by other tools to perform place-and-route, to create a physical layout of the circuit, and finally to generate the programming files that can be used to program the target device.

Read more on ASIC Design Flow.

To generate a 60% duty cycle clock using RTL code, we can use a counter to divide the input clock signal and use the output of the counter as the inverted output of a D-type flip-flop.

module clock_60_percent (
  input wire clk,
  input wire rst_n,
  output wire clk_60_percent
);

  // Define the maximum count value.
  // For a 60% duty cycle, we want the high time to be 3/5 of the period.
  // If the counter goes from 0 to 4 (5 states), we can have 'high' for 3 states and 'low' for 2 states.
  // So, MAX_COUNT = 4.
  localparam MAX_COUNT = 4;

  reg [2:0] counter; // Needs enough bits to represent MAX_COUNT

  // Duty cycle logic: HIGH for counter values 0, 1, 2 and LOW for 3, 4
  localparam HIGH_THRESHOLD = 3; // Counter values 0, 1, 2 will be HIGH

  assign clk_60_percent = (counter < HIGH_THRESHOLD) ? 1'b1 : 1'b0;

  always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
      counter <= 3'b0;
    end else begin
      if (counter == MAX_COUNT) begin
        counter <= 3'b0; // Reset counter
      end else begin
        counter <= counter + 1;
      end
    end
  end
endmodule          

To generate 100M clock with 50% duty cycle, we have to flip the clock bit every 5ns.

module tb;
	reg clk;

	initial clk = 0;   // without this, clk stays x forever
	// 1/100M = 10ns period 
	always #5 clk = ~clk;
endmodule

• `define

It is a preprocessor keyword that is used to define a text macro. It can be used to define constants, expressions or strings that can be used later in the code. When the Verilog/SystemVerilog compiler encounters a `define directive, it replaces the defined text with the macro value throughout the code before compilation.

`define MY_VALUE 4
always @(posedge clk) begin
   if (i == `MY_VALUE) begin
      // some code
   end
end

Here, MY_VALUE is a macro that has been defined with a value of 4. The macro is being used inside an always block to check if i is equal to 4. When this code is compiled, the preprocessor will expand the MY_VALUE macro into the actual value of 4.

• `include

It is also a preprocessor directive that is used to include a file in the current code. When the Verilog/SystemVerilog compiler encounters an `include statement, it reads the contents of the specified file and inserts them into the current source file at the location of the `include statement. The `include statement is mainly used to insert common code, libraries or modules into multiple files without copying the same code multiple times.

`include "my_file.v"
module my_module (input clk, input rst, output reg out);
   // some code
endmodule

Here, the `include statement is used to include the contents of the file `my_file.v` into the current module. The code inside my_file.v could contain module definitions, declarations, `define statements or other common code that can be reused in multiple modules.

A SystemVerilog program block holds testbench code. Its initial procedures run in the Reactive region, after the design's events in the same time step, which avoids races between testbench and design. A program can contain initial and final procedures, tasks, functions and declarations, but not always procedures, UDPs, or module, interface or program instances.

An always block is excluded because a program is expected to finish. When all of a program's initial procedures end, the program ends, and once every program has ended the simulator calls $finish. A free-running always block would prevent that.

FIFO (First-In-First-Out) is a type of buffer used in digital circuits to manage data transfer between devices or subsystems. It is a common design element in communication interfaces and memory management units. A FIFO stores data in a queue-like structure, where the first item that has been inserted into the buffer will be the first one to be removed.

Read more on Synchronous FIFO.

If there is no else part in an if-else statement, then execution will simply move on to the next statement after the if-else block, without executing any code when the if condition is false.

For example, consider the following Verilog code:

always @(posedge clk) begin
	if (data_ready) begin
  		data_valid <= 1;
	end
end

Because this block is clocked, the missing else is fine here: synthesis infers a flip-flop with an enable that holds data_valid when data_ready is low. The same omission in a combinational always block would infer a latch.

In a FIFO (First-In-First-Out) buffer, overflow and underflow occur when data is being added to or removed from the buffer and there is no space available to add new data (in the case of overflow) or no data available to remove (in the case of underflow).

Overflow occurs when new data is being written into the FIFO while it is full. This means that the buffer has reached its maximum capacity and cannot store any more data. In an overflowing FIFO, new data may overwrite the old data that is already in the FIFO, leading to data loss or corruption. This can cause serious issues in systems where data integrity is critical. To avoid overflow, a flag indicating whether the FIFO is full may be used.

Underflow, on the other hand, occurs when data is being read from the FIFO while it is empty. This means that there is no data available to remove from the buffer. When underflow occurs, the FIFO may return an invalid value or in some cases, return no value at all. To avoid underflow, a flag indicating whether the FIFO is empty may be used.

To minimize the impact of overflow and underflow, FIFOs are typically designed with a certain amount of headroom or slack, which is the difference between the maximum capacity of the FIFO and the actual data being stored. This allows the FIFO to accept some extra data without overflowing, and also allows for some data to be removed even if the buffer is not completely full. It's important to carefully choose the capacity of the FIFO to ensure that it can handle the maximum expected data rate in the system, while also providing enough slack to avoid overflow and underflow.

Also read on Synchronous FIFO.