Interview Question Bank

• Use a two-flop synchronizer: A two-flop synchronizer is a common technique used to safely transfer data between clock domains. It consists of two registers placed in series, both clocked by the destination clock domain, to ensure reliable transfer of data across domains.
• Be aware of clock skew: Clock skew can occur between different clock domains and can adversely affect the timing of the control signal. To mitigate this, compensate for the clock skew by adding a delay buffer.
• Consider using asynchronous FIFOs: Asynchronous FIFOs are used to transfer data between clock domains that have different clock frequencies. By implementing flow control and arbitration logic, asynchronous FIFOs can help avoid data loss, blocking, or lock-up.
• Simulate and verify: Always simulate and verify the design with all possible corner-case scenarios to ensure that control information is reliably transferred across different clock domains.

An asymmetrical FIFO is an ideal component for this purpose where the bus width between the write side and the read sides are different.

Read more on Synchronous FIFO.

When the write and read sides are running on different clock frequencies, a FIFO acts as a buffer thereby allowing the write side to simply push the transfer into the buffer instead of waiting for the slave to respond and the transfer to complete. This allows better utilization of the bus.

However, assume that the master posted data into the FIFO and assumed it to have completed. If the slave now issues an error, this condition will have to be routed back to the master somehow like an interrupt so it can resend the same transfer.

If the master aborts a read transaction late in the cyle when read prefetch has already taken place, then it is possible to get stale data from the FIFO, and contents may need to be flushed.

If a module has only inputs and no outputs, then the synthesis tool may throw empty modules with no logic or little logic.

Latches usually result when the tool cannot determine a unique value for a signal during synthesis. If the combinational logic in your RTL code is incomplete, contains uninitialized values, or does not have a defined output value for some input combination, the synthesis tool may generate latches to store the input signals' present values. If there are incomplete case or if else statements in the RTL code, the synthesis tool may generate latches to hold intermediate states until a valid condition is met.

Read more on Latch.

Combinatorial timing loops, also known as combinational feedback loops, are a type of timing issue that can occur in digital circuits. They happen when a logic path's output is fed back to its input without passing through any registers or flip-flops, creating an infinite loop that prevents the circuit from settling to a stable state. This means that the output of the circuit is undefined.

// A simple example shown below has output depedent on itself
// However, it can be complex with more logic in between but ultimately 
// feeding back to the same signal without any flops in between
assign out = out & in;

Combinatorial timing loops should be avoided in digital circuits for a few reasons:

• They can cause glitches: When a combinational loop exists, it creates a race condition where the output of the loop is dependent on the delays of the logic gates. Any small variation in these delays may cause the output of the circuit to glitch, leading to unpredictable behavior.
• They increase power consumption: When a combinational loop exists, the logic gates are continuously toggling outputs without settling to a stable state. This results in a high switching activity, which can increase the power consumption of the circuit.
• They increase the propagation delay: Combinatorial loops can lead to an increase in the circuit's propagation delay since the output of the loop depends on the previous output.

The sensitivity list of a combinatorial always block specifies the input signals to the block that trigger its execution. The sensitivity list informs the simulation tool which input signals to monitor for changes that would require an update in the output.

Verilog and SystemVerilog languages have evolved to allow designers represent their intentions more easily with new constructs.

// A normal sensitivity list should include all signals that affect output
always @ (a, b, c, d) begin
	out = (a & b) ^ (c | d);
end

// Use * to let tool automatically add such signals into the sensitivity list
always @ (*) begin
	out = (a & b) ^ (c | d);
end

// SystemVerilog has another keyword
always_comb begin
	out = (a & b) ^ (c | d);
end

The conditional compilation constructs, such as `ifdef, `ifndef, `elsif, and `endif, allow the designer to choose which part of the design is included in the synthesis process. This is useful when certain parts of the design are not necessary for the final implementation, and including them can result in an unnecessarily large area. By selectively including parts of the design, the synthesis tool can optimize the output circuit for a smaller size.

Read more on Verilog `ifdef Conditional Compilation.

Constant propagation is a compiler optimization technique that replaces the usage of variables with their constant values which helps reduce area and improve the performance of the synthesized circuit.

parameter zero = 0;

assign out = (zero == 1) ? in1 : in2;

In Verilog, constant propagation optimizes the circuit by replacing the values of variables that remain constant throughout the simulation with their final values. If a variable has a constant value, the synthesis tool optimizes the logic by replacing the variable with a wire that has the same constant value. This can help reduce the size of the synthesized circuit since fewer resources are required to implement the design.

Bits that are unused are optimized away during synthesis.

module design (...);

reg [3:0] tmp;

always @ (posedge clk) begin
	if (! resetn) begin
		tmp <= 0;
                
	// Since tmp[1] and tmp[2] are unused,
    // synthesized logic will contain only 2 flops
	end else begin
    	tmp[0] <= in;
		tmp[3] <= ~in;
	end
end

endmodule

The generate construct is a feature that allows designers to create multiple instances of a module or block of code.

It allows the use of a variable using genvar keyword to control the generated logic. It can have for loop, if else or case statements inside it for conditional generation of replicated hardware.

Read more on Verilog generate block.

• Use non-blocking assignments in always block triggered @ posedge clk
• Use positive edge triggered FF for state
• Do not assign the same variable in multiple always blocks
• Keep sequential and combinational blocks separate
• Do not mix blocking and non-blocking assignments in the same procedural block

No, the generate construct cannot be nested and will result in a syntax error if it is done so. But, if else, case conditional statements and for loops can be nested.

module design (...);

generate 
	...
	// Not allowed, results in error
	generate 
		...
	endgenerate
endgenerate

// Same module can have multiple independent
// generate blocks
generate 
...
endgenerate

generate
...
endgenerate

endmodule

Read more on Verilog generate block.

In a digital design, the critical path is the path of logic gates and interconnects that has the longest propagation delay, limiting the overall maximum operating frequency of the circuit. It is the slowest path of the combinational logic circuits that has the most significant impact on the performance of the design.

Accurately identifying the critical path is essential for timing analysis and avoiding timing violations, which can cause synchronization issues, glitches, or failures. Once the critical path is known, the designer can optimize it through techniques like pipelining, parallelism, or parallel paths to improve performance without affecting the design's functionality.

Partitioning the design refers to dividing a complex design into smaller sub-blocks that can be designed and analyzed separately to simplify the overall design.

Here are a few ways proper partitioning of a design can help:

• Reduces the complexity of timing analysis: Breaking down the design into smaller sub-blocks reduces the complexity required for the Static Timing Analysis (STA) and enables timing closure, making it easier to identify and fix the bugs.
• Enables parallel processing: Partitioned designs can be processed in parallel, thereby reducing the overall computation time. The designer can then optimize each sub-block independently for maximum utilization of computational resources.
• Enables design reuse: Partitioning the design allows for the reuse of the smaller sub-blocks in different designs, leading to reduced development time and cost.
• Reduces the critical path: Partitioning the design and optimizing each sub-block reduces their critical paths, ensuring multiple non-critical paths, which lowers the system's worst-case path delay and helps meet timing constraints.

Retiming is a technique used in digital circuit design to balance the path delay between sequential elements (registers) and combinational logic circuits. Retiming involves moving flip-flops so that the critical path is shifted to reduce its delay.

When correctly applied, retiming does not affect the functionality of the circuit. The circuit maintains its intended behavior, but the delay between the registers is redistributed, allowing for improvements in overall performance.

One-hot encoding is a technique used to encode state bits of a Finite State Machine (FSM) such that only one state bit is high (1) for each state. This encoding method is particularly useful for high-speed FSM designs due to the following reasons:

• Reduced delay and fast transition: In a one-hot encoded FSM, each state can be represented by a single flip-flop, and the next-state logic for each flip-flop depends on only a few state bits, which reduces propagation delay and ensures fast state transition times.
• Concurrent output generation: Each state corresponds to a unique output bit, so concurrent output generation is possible. This is because the current state can be determined without the propagation delay of a decoder, which enables faster clock speeds, improved throughput, and smaller critical paths.
• Easier timing closure: It makes the design simpler and less prone to timing violations which results in an easier timing closure .
• Reduced area and power consumption: Using a one-hot encoded FSM allows for easier implementation and requires fewer gates in the design, resulting in reduced area and power consumption.

Some factors include the presence of derived and gated clocks, latches and tri-state buses in the design.

Tri-state buses allow multiple devices to share data lines while minimizing the capacitance and current requirements for each device. The key issue with testing tri-state buses is to ensure that any open or stuck gates associated with the tri-state buses can be identified and tested effectively. These faults can cause contention or isolation errors, leading to intermittent or erratic behavior of the chip.

Some ways to improve testability are:

• Controlling the tri-state gates: To test the tri-state buses, it is essential to ensure that one device at a time is driving the bus. This can be achieved by controlling the tri-state gates and ensuring that all but one device is in the high-impedance state during the test.
• Using built-in self-test (BIST) circuitry: BIST circuitry can be added to the design to control and isolate the tri-state buses for testing. BIST circuitry can be used to scan in test patterns that will isolate and exercise each tri-state gate within the design.

During scan testing, if the driving FF gets a pattern such that it resets the driven FF, it will lose its data. Hence the reset output from the first FF should be OR'd with a test mode enable signal before assigning to the second FF.