Interview Question Bank

• Reset signal is not part of the data path in async-reset whereas reset signal is part of the D input of the FF in sync-reset.
• Effect of reset can happen anytime in async-reset whereas effect of reset will happen only on the active edge of a clock in sync-reset.
• Async-reset is prone to glitches where as sync-resets are safer in this regard.
• Async-reset needs to meet only the minimum reset pulse width for FF where as sync-reset has to be long enough to be sampled on the next clock edge.
• Async-reset input still needs the double FF synchronization to avoid race condition during reset de-assertion, while sync-reset do not need such additional circuitry.

When an integer is used as a storage element in a Verilog RTL code, it gets synthesized as a block of flip-flops similar to when a reg variable is used. Note that synthesis tool will optimize and remove unused flops.

module design (...);
	integer 	tmp;
	reg [7:0] 	data;

	always @ (posedge clk) begin
		// tmp [31:8] will be optimized because it is unused
		// since width of "data" is only 8b and so "tmp" does
		// not ever need anything more than 8b.
		tmp <= data; 	
	end
endmodule

However, the encoding and implementation of the flip-flops may differ between integers and regs, and this may affect the timing, area, and power consumption of the design. reg the recommended storage element for most RTL designs, as they are optimized for sequential logic operations and have predictable timing, area, and power consumption characteristics.

Read more on Verilog Data Types.

A case statement should be chosen to implement a multiplexer, whereas a multi-way if-else statement should be chosen to implement a priority encoder.

Note that if the default clause is missing in a case statement or all the possible cases are not specified then a latch is inferred. Similarly, for an if-else construct, a missing final else clause will infer a latch.

Read more on Verilog case and if-else-if statements.

The SystemVerilog keyword unique can be used which indicates that the order of decisions is not important and it would synthesize into parallel logic or multiplexer.

unique if (in[0]) sel = 0;
else if (in[1]) sel = 1;
else sel = 2;

Read more on SystemVerilog 'unique' and 'priority' case.

• Conditional operator is typically used in continuous assignments while if-else is used within procedural blocks.
• A true and false expression is always required for the conditional operator whereas else part is optional in the if construct.
• Conditional operators cannot have block statements with begin and end whereas if conditions can.

• Deeply nested conditional expressions are harder to understand whereas if statements are cleaner in this regard.

Read more on Verilog Conditional Statements.

The default clause is executed when none of the other cases are satisfied and if this is missing the logic will have to remember what the earlier value was and hence synthesis will infer a latch.

Read more on Verilog case statement.

In a clocked always block, a missing final else is legal and common. When no branch is taken the register keeps its value, so synthesis builds a flip-flop with a feedback mux or clock enable, and no warning is expected.

In a combinational always block, a missing final else means some input combinations assign nothing, so the output has to remember its old value and synthesis infers a latch. Add a final else, or assign default values at the top of the block, to keep the logic combinational.

Only logical equality/inequality operators (== and !=) are synthesizable. Case equality (===) and inequality (!==) operators also compare X and Z values, whereas logical comparison returns x when an x or z bit makes the result ambiguous.

When an x or z bit makes the comparison ambiguous, the logical equality and inequality operators return x, which an if statement treats as false. The case equality operators compare x and z bits literally and always return a known 0 or 1.

// If a or b has X/Z values (in addition to a!=b), 
// out will be driven a OR b
if (a == b) 
   	out = a & b; 	
else
	out = a | b;


// Both a and b match is done for 4-states
// out = a AND b only when a/b are both 0, 1, X or Z
if (a === b) 
	out = a & b;
else
	out = a | b;

casex has to be used when both X and Z needs to be treated as don't care for comparisons with the case item. casez on the other hand only treats Z as don't care.

casex (abc)
	3'bx00  : out = a & b; 		// same as 3'b000 and 3'b100
	3'b10x  : out = a | b; 		// same as 3'b100 and 3'b101
	default : out = ~(a & b); 	// all other values, such as 3'b011 or 3'b111
endcase

Here are a couple of advantages:

• Synthesis optimization: casex and casez can be optimized more effectively by synthesis tools than the case statement. This is because casex and casez allow for more efficient encoding of the match conditions, reducing the number of gates required to implement the logic.
• Code readability: casex and casez can make Verilog code more readable and concise. This is because they allow for more complex matching logic to be expressed in a single statement, rather than requiring multiple if-else statements.

Synchronous state machines have a clock input that triggers state transitions at specific times. When the clock signal rises, the state machine updates its output values and transitions to the next state based on its current state and input values.

Asynchronous state machines do not require a clock signal as they are triggered by input signals that are not synchronized in time. Each input signal can trigger a state transition at any time, independent of any clock signal. Asynchronous state machines can be more complex to design and test due to the possibility of race conditions and glitches, but they can be more efficient and consume less power compared to synchronous state machines.

Mealy State Machine:

• Outputs are a function of both current state and inputs.
• Output may not be stable for one clock cycle as it is a function of input and current state.
• Output is prone to glitches.
• State transitions are based on both the current state and input signals.
• If inputs are not registered, combinational paths could potentially be larger than Moore machine, less operating frequency.

Moore State Machine:

• Output is based solely on the current state
• Output is stable for one clock cycle.
• Output is not prone to glitches.
• State transitions depend on the current state and the inputs; only the outputs are independent of the inputs.
• Combinational paths are typically shorter with no involvement of inputs.

In binary encoding, each state is represented by a unique binary code, so n bits can encode up to 2ⁿ states. For example, if a state machine has four possible states, it can be represented using two bits (00, 01, 10, and 11).

• Binary encoding uses fewer flip-flops compared to one-hot encoding, which makes it more efficient in terms of hardware utilization.
• Timing is not as good as one-hot encoding due to more combinatorial paths
• Requires more effort for maintenance and debug
• Usually preferred in ASICs unless output path timing is critical

In one-hot encoding, each state is represented by a unique bit, with only one bit set to 1 and all other bits set to 0. For example, in a state machine with four possible states, each state is represented by a unique combination of four bits, with only one bit set to 1.

• The state transitions are clearly defined, which makes it easier to detect errors and glitches in the state machine
• One-hot encoding has a faster response time compared to binary encoding since next-state and output decoding only need to look at individual state bits
• It is easier to design and debug state machines using one-hot encoding
• Useful in register rich applications like FPGAs

A case expression can be a constant used to match against a variable also.

// 4-bit variable to store 4 states in one-hot encoding
reg [3:0] cur_state, next_state;

case (1'b1)
	cur_state[0] : // Assign next state 
	cur_state[1] : // Assign next state
	cur_state[2] : // Assign next state
	cur_state[3] : // Assign next state
endcase

Synchronous static memories that can be used like a register file can be defined as a multi-dimensional array which then gets synthesized into FFs. For the example below, each row of memory requires 8 FF, and with a depth of 16, the total FFs required will be 128.

parameter DEPTH = 16;
parameter WIDTH = 8;

reg [WIDTH-1:0] mem [DEPTH-1:0];

always @ (posedge clk) begin
	if (wr)
		mem[addr] <= i_data;
	else
		o_data <= mem[addr];                           
end	

Using a hardmacro of memory from a semiconductor vendor with better area and power would be better than synthesizing it using discrete logic.

When instantiating technology-specific memories, there are several key considerations to keep in mind to ensure optimal performance and efficiency:

• Area: A high density memory would be required to reduce area footprint of the design on the die, typically used by chips with large memory blocks.
• Frequency: Special high-speed memory cells that operate at high frequencies may be required if speed is the main concern, but it may have larger area.
• Power requirements: The power consumption of the memory should be considered, especially in low-power applications. Memories such as DRAM and SRAM typically require low power, while NAND flash memory requires higher power.
• Memory type: Depending on the application, the appropriate memory technology should be selected, such as SRAM, DRAM, or flash memory, each with their own advantages and disadvantages.
• Memory access speed: The memory access speed should be chosen based on the performance requirements of the system. DDR memory provides high-speed access, whereas NOR flash memory provides fast read access.
• Pinout and package options: The pinout and package options should be selected based on the available space and required signal requirements of the system.
• Single vs Multi Port: Depends on overall design architecture required to support a targeted performance of the system. Multiple ports allow write and read transactions to happen concurrently thereby boosting its performance.
• Voltage requirements: The voltage requirements of the memory should also be taken into account to ensure compatibility with the power supply and other components in the system.
• Cost: The cost of the memory should be evaluated against the benefits provided to ensure that it is a cost-effective solution.

• Performance: Synchronous memories are generally faster than asynchronous memories and synchronize data transfer with a clock signal. For applications that require high-speed data transfer, synchronous memory is the better choice.
• Latency: Asynchronous memories typically have higher read and write latencies whereas synchronous memories have predictable latencies and faster cycle times. Asynchronous memories may be acceptable for applications that can tolerate higher latencies.
• Power Consumption: Asynchronous memories typically consume less power compared to synchronous memories since there's no internal clock signal making them desirable for power-sensitive applications.
• Timing: Synchronous memories have better static timing because data output is registered with a FF, whereas asynchronous memories have combinatorial paths that may become critical element in the timing path.
• Area: Synchronous memories require more area compared to asynchronous memories.
• Noise immunity: Synchronous memory has better noise immunity compared to asynchronous memory. The use of the clock signal makes it less vulnerable to electrical noise and other forms of interference.
• Cost: Asynchronous memories are less complex and easier to manufacture, making them more cost-effective compared to synchronous memories.

• Better timing closure can be achieved if all outputs of critical design blocks are registered.
• Avoid snake paths which make debugging tedious and synthesis difficult.
• Avoid instantiation of technology specific gates.
• Use parameters and macros instead of hard-coded values in design RTL.
• Breaking down functionality into smaller submodules can help to minimize the complexity of your code, which makes it more reusable.
• Use generic RTL code is general-purpose code that can be reused in many different applications.
• Develop your coding style to facilitate readability and maintenance. Consistent coding practices, such as standard naming conventions and formatting, can make your code more understandable and reusable.
• Intellectual property (IP) modules are proven, tested designs that have been created for reuse. Reusing IP modules can minimize the development time, cost, and risk associated with designing from scratch.
• Utilizing a standardized library with commonly used functions makes it easier to design and maintain RTL code across multiple projects.

It is a path that goes through different levels of hierarchies and return to the same level where it started from. These should be avoided because it will have a long timing path and may turn out to be a critical path in chip top, and synthesis tools will have harder time to constrain paths leading to larger runtimes.

To avoid this:

• Register the outputs of modules with different functional objectives
• Partition the design functionality, and aim for short and direct routes between components.

• Size and complexity of the design: A large design will need to be partitioned into a number of smaller designs. This can affect how the design is divided into different sections and the size of each partition.
• Clock Domains: It is recommended to group logic belonging to same clock domain in a single block, and clock domain crossings done thorugh a synchronizer.
• Specific design requirements: Specific design requirements, such as timing or power constraints, will affect how the design is partitioned.
• Vendor's requirements: The vendor's requirements must also be considered as the partitioning of designs will be determined largely by their manufacturing capabilities.