UVM TLM ports and exports are also used to send transaction objects cross different levels of testbench hierarchy.
Ports shall be used to initiate and forward packets to the top layer of the hierarchy. Exports shall be used to accept and forward packets from the top layer to destination. Implementation ports shall be used to define the put method at the target. Shown below are a few examples that use ports, exports and implementation for components at different hierarchy levels.
Port to Port to Export to Imp
subCompA is a subcomponent within componentA that is trying to send transactions to another subcomponent called subCompB in componentB. To maintain flexibility and portability of code, it is recommended to allow subCompA to send data to componentA which should then forward them to the top layer of the hierarchy. componentB shall accept the transaction and forward it to subCompB.
A class called Packet is defined below to act as the data item that will be transferred from one component to another. This class object will have two random variables that can be randomized before sending.
// Create a class data object that can be sent from one
// component to another
class Packet extends uvm_object;
rand bit[7:0] addr;
rand bit[7:0] data;
`uvm_object_utils_begin(Packet)
`uvm_field_int(addr, UVM_ALL_ON)
`uvm_field_int(data, UVM_ALL_ON)
`uvm_object_utils_end
function new(string name = "Packet");
super.new(name);
endfunction
endclass
Subcomponent A
class subCompA extends uvm_component;
`uvm_component_utils (subCompA)
function new(string name, uvm_component parent);
super.new(name, parent);
endfunction
uvm_blocking_put_port #(Packet) m_put_port;
int m_num_tx=2;
virtual function void build_phase(uvm_phase phase);
super.build_phase(phase);
m_put_port = new ("m_put_port", this);
endfunction
// Create a packet, randomize it and send it through the port
// Note that put() is a method defined by the receiving component
// Repeat these steps N times to send N packets
virtual task run_phase (uvm_phase phase);
phase.raise_objection(this);
repeat (m_num_tx) begin
Packet pkt = Packet::type_id::create ("pkt");
assert(pkt.randomize ());
// Print the packet to be displayed in log
`uvm_info ("SUBCOMPA", "Packet sent to subCompB", UVM_LOW)
pkt.print (uvm_default_line_printer);
// Call the TLM put() method of put_port class and pass packet as argument
m_put_port.put (pkt);
end
phase.drop_objection(this);
endtask
endclass
Component A
class componentA extends uvm_component;
`uvm_component_utils (componentA)
function new (string name = "componentA", uvm_component parent= null);
super.new (name, parent);
endfunction
subCompA m_subcomp_A;
uvm_blocking_put_port #(Packet) m_put_port;
virtual function void build_phase(uvm_phase phase);
super.build_phase(phase);
m_subcomp_A = subCompA::type_id::create("m_subcomp_A", this);
m_put_port = new ("m_put_port", this);
endfunction
// Connection with subCompA
virtual function void connect_phase(uvm_phase phase);
super.connect_phase(phase);
m_subcomp_A.m_put_port.connect(this.m_put_port);
endfunction
endclass
Component B
class componentB extends uvm_component;
`uvm_component_utils (componentB)
function new(string name, uvm_component parent);
super.new(name, parent);
endfunction
subCompB m_subcomp_B;
uvm_blocking_put_export#(Packet) m_put_export;
virtual function void build_phase(uvm_phase phase);
super.build_phase(phase);
m_subcomp_B = subCompB::type_id::create("m_subcomp_B", this);
m_put_export = new("m_put_export", this);
endfunction
// Connection with subCompB
virtual function void connect_phase(uvm_phase phase);
m_put_export.connect(m_subcomp_B.m_put_imp);
endfunction
endclass
Subcomponent B
class subCompB extends uvm_component;
`uvm_component_utils (subCompB)
function new (string name = "subCompB", uvm_component parent = null);
super.new (name, parent);
endfunction
// Mention type of transaction, and type of class that implements the put ()
uvm_blocking_put_imp #(Packet, subCompB) m_put_imp;
virtual function void build_phase (uvm_phase phase);
super.build_phase (phase);
m_put_imp = new ("m_put_imp", this);
endfunction
// Implementation of the 'put()' method in this case simply prints it.
virtual task put (Packet pkt);
`uvm_info ("SUBCOMPB", "Packet received from subCompA", UVM_LOW)
pkt.print(uvm_default_line_printer);
endtask
endclass
class my_test extends uvm_test;
`uvm_component_utils (my_test)
componentA compA;
componentB compB;
function new (string name = "my_test", uvm_component parent = null);
super.new (name, parent);
endfunction
// Create objects of both components, set number of transfers
virtual function void build_phase (uvm_phase phase);
super.build_phase (phase);
compA = componentA::type_id::create ("compA", this);
compB = componentB::type_id::create ("compB", this);
endfunction
// Connection between componentA and componentB is done here
virtual function void connect_phase (uvm_phase phase);
compA.m_put_port.connect (compB.m_put_export);
endfunction
virtual function void end_of_elaboration_phase(uvm_phase phase);
super.end_of_elaboration_phase(phase);
uvm_top.print_topology();
endfunction
endclass
Simulation Log
UVM_INFO @ 0: reporter [RNTST] Running test my_test...
UVM_INFO /playground_lib/uvm-1.2/src/base/uvm_root.svh(579) @ 0: reporter [UVMTOP] UVM testbench topology:
------------------------------------------------------
Name Type Size Value
------------------------------------------------------
uvm_test_top my_test - @1842
compA componentA - @1911
m_put_port uvm_blocking_put_port - @2008
m_subcomp_A subCompA - @1974
m_put_port uvm_blocking_put_port - @2047
compB componentB - @1942
m_put_export uvm_blocking_put_export - @2115
m_subcomp_B subCompB - @2081
m_put_imp uvm_blocking_put_imp - @2152
------------------------------------------------------
UVM_INFO testbench.sv(71) @ 0: uvm_test_top.compA.m_subcomp_A [SUBCOMPA] Packet sent to subCompB
pkt: (Packet@2191) { addr: 'h24 data: 'h31 }
UVM_INFO testbench.sv(151) @ 0: uvm_test_top.compB.m_subcomp_B [SUBCOMPB] Packet received from subCompA
pkt: (Packet@2191) { addr: 'h24 data: 'h31 }
UVM_INFO testbench.sv(71) @ 0: uvm_test_top.compA.m_subcomp_A [SUBCOMPA] Packet sent to subCompB
pkt: (Packet@2209) { addr: 'h9a data: 'hfb }
UVM_INFO testbench.sv(151) @ 0: uvm_test_top.compB.m_subcomp_B [SUBCOMPB] Packet received from subCompA
pkt: (Packet@2209) { addr: 'h9a data: 'hfb }
UVM_INFO /playground_lib/uvm-1.2/src/base/uvm_objection.svh(1271) @ 0: reporter [TEST_DONE] 'run' phase is ready to proceed to the 'extract' phase
UVM_INFO /playground_lib/uvm-1.2/src/base/uvm_report_server.svh(847) @ 0: reporter [UVM/REPORT/SERVER]
--- UVM Report Summary ---
Port to Port to Imp
In this example componentA forwards the packet from subCompA to the destination componentB. The only difference is that componentB is the target and hence should define the implementation port instead of an export.
// componentB shall implement "put" and there's no subCompB
class componentB extends uvm_component;
`uvm_component_utils (componentB)
function new(string name, uvm_component parent);
super.new(name, parent);
endfunction
uvm_blocking_put_imp#(Packet, componentB) m_put_imp;
virtual function void build_phase(uvm_phase phase);
super.build_phase(phase);
m_put_imp = new("m_put_imp", this);
endfunction
// Implementation of the 'put()' method in this case simply prints it.
virtual task put (Packet pkt);
`uvm_info ("COMPB", "Packet received from subCompA", UVM_LOW)
pkt.print(uvm_default_line_printer);
endtask
endclass
Simulation Log
UVM_INFO @ 0: reporter [RNTST] Running test my_test...
UVM_INFO /playground_lib/uvm-1.2/src/base/uvm_root.svh(579) @ 0: reporter [UVMTOP] UVM testbench topology:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
uvm_test_top my_test - @1839
compA componentA - @1908
m_put_port uvm_blocking_put_port - @2005
m_subcomp_A subCompA - @1971
m_put_port uvm_blocking_put_port - @2044
compB componentB - @1939
m_put_imp uvm_blocking_put_imp - @2081
----------------------------------------------------
UVM_INFO testbench.sv(70) @ 0: uvm_test_top.compA.m_subcomp_A [SUBCOMPA] Packet sent to CompB
pkt: (Packet@2119) { addr: 'h24 data: 'h31 }
UVM_INFO testbench.sv(124) @ 0: uvm_test_top.compB [COMPB] Packet received from subCompA
pkt: (Packet@2119) { addr: 'h24 data: 'h31 }
UVM_INFO testbench.sv(70) @ 0: uvm_test_top.compA.m_subcomp_A [SUBCOMPA] Packet sent to CompB
pkt: (Packet@2133) { addr: 'h9a data: 'hfb }
UVM_INFO testbench.sv(124) @ 0: uvm_test_top.compB [COMPB] Packet received from subCompA
pkt: (Packet@2133) { addr: 'h9a data: 'hfb }
UVM_INFO /playground_lib/uvm-1.2/src/base/uvm_objection.svh(1271) @ 0: reporter [TEST_DONE] 'run' phase is ready to proceed to the 'extract' phase
UVM_INFO /playground_lib/uvm-1.2/src/base/uvm_report_server.svh(847) @ 0: reporter [UVM/REPORT/SERVER]
--- UVM Report Summary ---
Port to Export to Imp
In this example componentA is the initiator and sends a packet from its port to the destination subCompB which implements the put method. Since componentB is the container for the target, it should have an export to forward the packets received from the connected port at the top level.
// componentA will start transactions and send to its port
class componentA extends uvm_component;
`uvm_component_utils (componentA)
function new (string name = "componentA", uvm_component parent= null);
super.new (name, parent);
endfunction
uvm_blocking_put_port #(Packet) m_put_port;
int m_num_tx=2;
virtual function void build_phase(uvm_phase phase);
super.build_phase(phase);
m_put_port = new ("m_put_port", this);
endfunction
// Create a packet, randomize it and send it through the port
// Note that put() is a method defined by the receiving component
// Repeat these steps N times to send N packets
virtual task run_phase (uvm_phase phase);
phase.raise_objection(this);
repeat (m_num_tx) begin
Packet pkt = Packet::type_id::create ("pkt");
assert(pkt.randomize ());
// Print the packet to be displayed in log
`uvm_info ("SUBCOMPA", "Packet sent to subCompB", UVM_LOW)
pkt.print (uvm_default_line_printer);
// Call the TLM put() method of put_port class and pass packet as argument
m_put_port.put (pkt);
end
phase.drop_objection(this);
endtask
endclass
Simulation Log
UVM_INFO @ 0: reporter [RNTST] Running test my_test...
UVM_INFO /playground_lib/uvm-1.2/src/base/uvm_root.svh(579) @ 0: reporter [UVMTOP] UVM testbench topology:
------------------------------------------------------
Name Type Size Value
------------------------------------------------------
uvm_test_top my_test - @1839
compA componentA - @1908
m_put_port uvm_blocking_put_port - @1974
compB componentB - @1939
m_put_export uvm_blocking_put_export - @2044
m_subcomp_B subCompB - @2010
m_put_imp uvm_blocking_put_imp - @2081
------------------------------------------------------
UVM_INFO testbench.sv(73) @ 0: uvm_test_top.compA [SUBCOMPA] Packet sent to subCompB
pkt: (Packet@2120) { addr: 'ha1 data: 'h64 }
UVM_INFO testbench.sv(127) @ 0: uvm_test_top.compB.m_subcomp_B [SUBCOMPB] Packet received from subCompA
pkt: (Packet@2120) { addr: 'ha1 data: 'h64 }
UVM_INFO testbench.sv(73) @ 0: uvm_test_top.compA [SUBCOMPA] Packet sent to subCompB
pkt: (Packet@2134) { addr: 'hc1 data: 'hb9 }
UVM_INFO testbench.sv(127) @ 0: uvm_test_top.compB.m_subcomp_B [SUBCOMPB] Packet received from subCompA
pkt: (Packet@2134) { addr: 'hc1 data: 'hb9 }
UVM_INFO /playground_lib/uvm-1.2/src/base/uvm_objection.svh(1271) @ 0: reporter [TEST_DONE] 'run' phase is ready to proceed to the 'extract' phase
UVM_INFO /playground_lib/uvm-1.2/src/base/uvm_report_server.svh(847) @ 0: reporter [UVM/REPORT/SERVER]
--- UVM Report Summary ---
Port to Port to Export to Export to Imp
In this example there is an additional layer between componentB and the target subCompB2 called subCompB1. This layer has to simply forward the packet to the destination and hence shall have an export.
Simulation Log
UVM_INFO @ 0: reporter [RNTST] Running test my_test...
UVM_INFO /playground_lib/uvm-1.2/src/base/uvm_root.svh(579) @ 0: reporter [UVMTOP] UVM testbench topology:
--------------------------------------------------------
Name Type Size Value
--------------------------------------------------------
uvm_test_top my_test - @1845
compA componentA - @1914
m_put_port uvm_blocking_put_port - @2011
m_subcomp_A subCompA - @1977
m_put_port uvm_blocking_put_port - @2050
compB componentB - @1945
m_put_export uvm_blocking_put_export - @2118
m_subcomp_B1 subCompB1 - @2084
m_put_export uvm_blocking_put_export - @2186
m_subcomp_B2 subCompB2 - @2152
m_put_imp uvm_blocking_put_imp - @2223
--------------------------------------------------------
UVM_INFO testbench.sv(75) @ 0: uvm_test_top.compA.m_subcomp_A [SUBCOMPA] Packet sent to subCompB
pkt: (Packet@2262) { addr: 'h24 data: 'h31 }
UVM_INFO testbench.sv(179) @ 0: uvm_test_top.compB.m_subcomp_B1.m_subcomp_B2 [SUBCOMPB2] Packet received from subCompA
pkt: (Packet@2262) { addr: 'h24 data: 'h31 }
UVM_INFO testbench.sv(75) @ 0: uvm_test_top.compA.m_subcomp_A [SUBCOMPA] Packet sent to subCompB
pkt: (Packet@2284) { addr: 'h9a data: 'hfb }
UVM_INFO testbench.sv(179) @ 0: uvm_test_top.compB.m_subcomp_B1.m_subcomp_B2 [SUBCOMPB2] Packet received from subCompA
pkt: (Packet@2284) { addr: 'h9a data: 'hfb }
UVM_INFO /playground_lib/uvm-1.2/src/base/uvm_objection.svh(1271) @ 0: reporter [TEST_DONE] 'run' phase is ready to proceed to the 'extract' phase
UVM_INFO /playground_lib/uvm-1.2/src/base/uvm_report_server.svh(847) @ 0: reporter [UVM/REPORT/SERVER]
--- UVM Report Summary ---
