Learning Path by Role

After the common foundation, each chip role builds its own set of skills. A verification engineer goes deep into SystemVerilog and UVM, a physical designer into placement, routing and timing, an architect into performance modeling. This article gives a learning order for each digital role described in this tutorial, points to the ChipVerify tutorials that cover each step, lists the open-source tools that let you practise the whole flow for free, and ends with a ladder of projects to build experience.

9 min read | Beginner

What You'll Learn

• Choose a learning order for the role you are aiming at
• Map each step to a ChipVerify tutorial
• List the open-source tools that cover the flow from RTL to layout
• Plan a ladder of projects from small blocks to a full flow run

Start From the Shared Base

Every path below assumes the foundation from The Common Foundation for Chip Careers: Digital Fundamentals, Verilog, Linux and a scripting language. Most engineers go deep in one track and learn enough of the neighbouring ones to work with them, because the roles share the same design database: a timing failure found in physical design often becomes an RTL change, and a bug found in verification becomes a design fix and a new netlist. The paths are suggestions in a sensible order, not requirements; the role articles in this tutorial describe what postings actually ask for.

Verification

Verification postings ask for SystemVerilog, UVM, constrained-random testing, coverage and assertions, with formal verification and emulation as specialties^[1][2]. A learning order that follows those skills:

A habit worth starting even with plain Verilog is the self-checking testbench: apply many random inputs, compare the design's output with a reference model, count mismatches and print PASS or FAIL at the end. Every later verification method builds on that idea.

RTL Design

RTL design postings ask for micro-architecture, synthesizable Verilog or SystemVerilog, clock domain crossing, area and power trade-offs, and synthesis and timing closure^[3][4]. Beyond the language, the path goes through the topics that separate working RTL from good RTL: pipelining, handshakes and FIFOs; clock domain crossing and reset design; clock gating and power intent in Unified Power Format; and reading the reports of RTL Synthesis and Static Timing Analysis, so you know what hardware each construct becomes. SoC Design shows how blocks are integrated into a chip.

Architecture and Performance Modeling

Architecture and performance postings ask for computer architecture, C++ or SystemC performance models, power and performance analysis and, often, an advanced degree^[5][6]. Start with Computer Architecture for caches, pipelines and memory, continue with SoC Design for interconnects and system trade-offs, and practise modeling in C++ or Python alongside.

Physical Design, Timing and DFT

Implementation postings expect the flow from netlist to layout: floorplanning, placement, clock tree synthesis, routing and timing closure, plus scripting in Tcl and Python^[7][8]. DFT postings add scan insertion, ATPG and test compression^[9]. A learning order:

Silicon Validation, Test and Product

Post-silicon validation postings ask for bring-up and debug of real chips with SoC knowledge and scripting; product and test engineering postings add characterization, test programs on automatic test equipment and yield improvement^[10][11]. Post-Silicon Validation covers bring-up and debug, building on SoC Design and Bus Protocols.

FPGA, CAD and Tools

FPGA postings combine RTL design with vendor tools, timing constraints and validation on hardware^[12], so the RTL design path applies, with timing constraints early. CAD and EDA development postings ask for strong software skills, Python, Tcl and C++, and knowledge of the flows the tools serve^[13][14]: learn the flow from synthesis to layout, then automate it.

Analog and Mixed-Signal

This site covers modern digital workflows. Analog and mixed-signal careers follow a different path through circuit theory, device physics, transistor-level simulation and layout, described in Analog and Mixed-Signal Roles. The digital tutorials still help analog engineers who work on mixed-signal verification or with digital neighbours.

Practising With Open-Source Tools

Professional chip design uses commercial simulators, synthesis and place-and-route tools, whose licences are usually only available through employers or universities. Open-source tools cover the whole flow from RTL to a real layout:

These tools are not only for hobbyists. A paper from Infineon and university co-authors compared them with commercial tools on RISC-V designs: commercial tools gave better quality of results and shorter runtimes, but OpenROAD was found a good trade-off of results, cost and transparency^[15]. An ETH Zurich team used an open-source flow to implement Basilisk, a Linux-booting 64-bit RISC-V SoC with millions of gates^[16].

A first synthesis run with Yosys takes a few commands:

# Yosys: synthesize a design to a standard-cell library and report its size
read_verilog counter.v
synth -top counter              # generic synthesis and optimization
dfflibmap -liberty cells.lib    # map flip-flops to library cells
abc -liberty cells.lib          # map combinational logic to library cells
stat -liberty cells.lib         # report cell counts and area
write_verilog counter_netlist.v # write the gate-level netlist

Installing and connecting each tool takes time. ChipVerify Lab has the flow set up in the browser: simulation and waveforms, synthesis to a 130 nm standard-cell library, timing analysis, place and route and the final layout.

A Project Ladder

Each project should include the RTL, a self-checking testbench and a synthesis run, so that it exercises design, verification and implementation together:

Verification-focused learners can rebuild the testbenches of the same projects in SystemVerilog and then UVM; implementation-focused learners can push the same designs through timing closure at higher clock targets. Building a Portfolio and Getting Experience covers how to present this work.

Summary

• Every path starts from digital logic, Verilog, Linux and scripting, then goes deep in one track.
• Verification goes through SystemVerilog, methodology, UVM and formal; RTL design through micro-architecture, CDC, low power, synthesis and timing.
• Implementation goes from synthesis through timing, layout, power and test.
• Open-source tools from Icarus and Yosys to OpenROAD and KLayout cover the whole flow and are used in industrial and research work.
• A ladder of projects, each with RTL, testbench and synthesis, builds experience across tracks.

Sources

1. Design verification engineer, Selby Jennings.
2. SystemVerilog/UVM design verification engineer, Jobgether.
3. Senior staff RTL design engineer, Synopsys.
4. RTL design engineer, AMD posting via Hitmarker.
5. Client SoC performance architect, Intel.
6. SoC performance analysis engineer, Arm.
7. Physical design engineer, Wipro.
8. STA engineer, AMD posting via Hitmarker.
9. Senior DFT engineer, Capgemini.
10. Post-silicon validation and methodology engineer, Nvidia posting via AnitaB.org.
11. Staff product development engineer, silicon test and yield, AMD posting via Hitmarker.
12. Senior FPGA engineer, Applied Materials.
13. CAD/flow methodology development, Tylsemi posting via Built In.
14. R&D engineer, C/C++, Synopsys.
15. Using open-source EDA tools in an industrial design flow, DVCon proceedings.
16. Insights from Basilisk: are open-source EDA tools ready for a multi-million-gate, Linux-booting RV64 SoC design?, arXiv.