A complex chip takes roughly one to two years of design work[1], and many specialists own small pieces of that journey. Job titles such as "DV engineer" or "PD engineer" only make sense once you see where in the journey each one works, what they receive and what they hand on. This article follows a chip from its first requirements to working silicon, stage by stage, names the roles at each step, and gives the industry's measured figures on how the effort is split.
9 min read | Beginner
What You'll Learn
- Follow a chip project from requirements to working silicon
- Name the engineering roles at each stage and what they produce
- Explain how effort is split between design and verification
- Explain where analog and mixed-signal engineers fit in a chip project
- Describe how post-silicon validation works with the earlier teams
The Journey in Brief
Every chip passes through the same broad stages: decide what to build, describe it in a hardware language, check that the description is right, turn it into a physical layout, manufacture it, and check the real parts. ASIC Design Flow explains each stage technically. Here the focus is on the people at each stage.
| Stage | Main roles | What they produce |
|---|---|---|
| Requirements and architecture | architects, performance modelers | the architecture spec, performance and power budgets |
| Design | RTL design engineers, IP integrators | RTL code for each block and the top level |
| Verification | design verification, formal and emulation engineers | test environments, coverage results, bug reports |
| Analog and mixed-signal | AMS design and analog layout engineers | converters, PLLs, high-speed transceivers, power circuits and their layouts |
| Test insertion | DFT engineers | scan, memory test and test patterns |
| Implementation | synthesis, physical design and timing engineers | the final layout, timing and power sign-off |
| Manufacturing | foundry, packaging and product engineers | packaged, tested chips |
| Bring-up and validation | post-silicon validation, software and application engineers | working silicon, drivers, characterization data |
The SoC Team and Flow in the SoC Design tutorial describes the same phases from the project's point of view.
Requirements and Architecture
A project starts with what the product must do. Architects turn those needs into a plan: which blocks the chip has, how they connect, and what performance, power and area it can afford. Performance modelers build software models that predict whether the plan meets its targets before anything is designed.
Architecture is a senior role. Job postings for SoC architects in 2025 and 2026 commonly ask for ten or more years of chip development experience, and those for verification architects ask for a similar amount of verification experience[2]. Most architects therefore come from design or verification work.
Design
RTL design engineers describe each block's logic in a hardware description language such as Verilog or SystemVerilog, and others integrate blocks, many of them licensed IP, into the top level of the chip. Design job postings typically ask for RTL coding experience plus working knowledge of the neighboring steps: synthesis, test insertion, verification, formal methods and silicon debug[2].
Verification
Design verification (DV) engineers check that the RTL does what the spec says before anything is built. They write test environments, often in SystemVerilog with UVM, run large numbers of tests and measure coverage. Formal verification engineers prove properties mathematically, and emulation engineers run the design on special hardware fast enough to boot software.
The industry's largest regular survey of chip projects gives the most detailed picture of this work[3][4]:
- Across most kinds of chips, projects have roughly as many verification engineers as design engineers at their peak; on processor projects, verification engineers can outnumber designers five to one.
- The number of verification engineers per project grew more than twice as fast as the number of designers between 2007 and 2022.
- Design engineers themselves spend close to half their time on verification.
- In 2024, only 14 percent of projects produced working silicon on the first attempt, down from 32 percent in 2020 and the lowest share in about twenty years.
The study's author puts verification at about 60 to 70 percent of the engineering effort on a chip project[5]. That share is why AI tools aimed at verification have attracted so much attention, as Where AI Is Used in Chip Design Today explains.
Quick Check
Q: A project's design team peaks at six engineers. Based on the survey figures, how many verification engineers might it have at its peak?
Show Answer
Around six for most kinds of chips, since the survey found a roughly one-to-one ratio at peak. On a processor project the ratio can reach five to one, which would mean around thirty.
Test Insertion
Every manufactured chip is tested for defects. DFT engineers, design for test, add the structures that make that possible, such as scan chains, memory self-test and test access ports, and generate the patterns that test equipment applies. Design for Test at SoC Level explains the techniques.
Implementation
Physical design (PD) engineers turn the verified netlist into a layout: floorplanning, placement, clock tree and routing. Timing engineers run static timing analysis and make every path meet its requirements. Others check power delivery and manufacturing rules. The work ends at tape-out, when the final layout goes to the foundry. The Physical Design and Static Timing Analysis tutorials cover this stage.
Implementation is where AI-based optimization reached production first. By early 2023, one EDA vendor reported 100 commercial tape-outs that had used its AI-driven optimization of design settings[6], and another vendor reports more than 300 tape-outs with its equivalent tool[7].
Analog and Mixed-Signal Engineers
Not every circuit on a chip is digital. Analog and mixed-signal (AMS) engineers design circuits that work with continuous voltages and currents: data converters, phase-locked loops that generate clocks, the transceivers of high-speed interfaces, power management circuits and I/O. Job postings for these roles describe transistor-level design and simulation with circuit simulators, and separate analog layout roles draw the physical layout of these circuits. Postings often ask for five or more years of experience[8].
Their flow differs from the digital one. Digital layout is almost completely automated, while analog layout is still largely done by hand and depends heavily on the engineer's expertise[9]. EDA vendors began offering AI-based analog layout tools in 2026, with early, vendor-reported speedups, so this may change[10]. On a chip, analog circuits usually arrive as finished layout blocks that the digital teams place and connect, as Buy, Reuse or Build: Choosing IP describes. Market research lists analog and mixed-signal design among the specialties with the fewest available engineers[11].
ChipVerify, including this tutorial's later chapters, focuses on modern digital design and verification: RTL, verification, synthesis, timing, physical design and test. Analog work is described here so that you know where it fits, but its methods are not taught on this site.
Where Is This Used?
Large projects spread these stages across countries. One report estimates that about 20 percent of the world's chip design engineers are based in India, and describes a common arrangement in which teams in the United States set much of the high-level architecture while teams in India do much of the design, verification and implementation work[12]. As of early 2026, about 180 design centers of global chip companies in India employed more than 110,000 people[13].
Manufacturing, Bring-Up and Validation
After tape-out, the foundry makes the wafers and packaging and test companies finish the parts. Product and test engineers develop production tests and work on yield. When the first chips return, post-silicon validation engineers bring them up: they power them on, run tests across voltage and temperature, and debug failures. Software teams bring up drivers and firmware, and application engineers help customers use the chip.
Validation is usually done by a dedicated team rather than by the engineers who wrote the RTL. Validation job postings describe that team working with the architecture, design and verification teams: reproducing silicon failures on emulators and FPGAs together with the verification team, and proposing debug features for future chips to the design team. In smaller companies, pre-silicon verification engineers are often part of validation as well[14][15].
How the Stages Overlap
The stages overlap in time. Verification starts as soon as the first RTL exists, implementation runs trial layouts on early versions of the design, and software work starts on models and emulators before silicon arrives. Each team therefore works with versions of its inputs that are still changing.
Quick Check
Q: A validation team finds that a chip hangs when a DMA transfer and a power-down happen together. Which other teams are likely to be involved in finding the cause?
Show Answer
The verification team, to reproduce the failure on an emulator or FPGA, and the designers of the DMA engine and the power controller, to find and fix the cause. The validation team leads the debug on silicon.
Summary
- A chip passes through architecture, design, verification, test insertion, implementation, manufacturing and validation, each with its own roles.
- Projects have roughly as many verification as design engineers at peak, and many more on processor projects.
- Only 14 percent of projects had working first silicon in 2024, down from 32 percent in 2020.
- AI-based optimization has been used in commercial tape-outs since the early 2020s, first in implementation.
- Analog and mixed-signal engineers design converters, clocks, transceivers and power circuits with a largely manual flow; this site focuses on the digital flow.
- Validation is usually a dedicated team that works with verification and design to debug silicon.
Sources
- SoC design cost and schedule estimates, Semico Research; How much will that chip cost?, Semiconductor Engineering.
- SoC architect, verification architect and SoC design job postings, 2025 to 2026 (for example Openchip SoC architecture engineer and SoC architect posting, Hyderabad).
- Part 8: The 2022 Wilson Research Group functional verification study, Siemens Verification Horizons (engineer ratios and headcount growth).
- 2024 Wilson Research Group IC/ASIC functional verification trend report, Siemens EDA (first-silicon success, time spent on verification).
- Why first silicon success is getting harder for system companies, Siemens Verification Horizons, September 2025.
- AI-designed chips reach scale with first 100 commercial tape-outs, Synopsys press release, February 2023.
- Cadence Cerebrus in SaaS: case study, Cadence.
- Analog and mixed-signal design job postings, 2026 (for example Analog Devices mixed-signal design engineer).
- The 6 requirements of effective analog layout automation, Cadence blog; analog layout automation thesis, UCLA.
- Introducing AI-powered analog layout synthesis, Synopsys blog, 2026.
- Semiconductor design market report, Fortune Business Insights.
- Around 20% of world's chip design engineers based in India, The Tribune (Bastion Research report).
- Semiconductor GCC hiring in India rises to 3,549 open roles in Q1 2026, The Hans India (Careernet report).
- Post-silicon validation, ChipVerify.
- Post-silicon validation job postings, 2025 to 2026 (for example Nvidia post-silicon validation and methodology engineer).
