Entry-level chip roles ask for skills that are hard to show on a transcript: writing RTL that synthesizes, building a testbench that finds bugs, closing timing on a real layout. A portfolio of projects, internships and, increasingly, real chips taped out through shared shuttles lets students and career changers show those skills before their first job. This article covers what to build, how to present it, where experience can be gained outside a job, and what the first tasks in a job usually look like.
7 min read | Beginner
What You'll Learn
- Choose projects that demonstrate the skills a target role asks for
- Present a project so a reviewer can check it quickly
- Describe the routes to real silicon, internships and training programmes
- Set expectations for the first tasks in an entry-level role
What a Portfolio Needs to Show
Entry postings list the same skills as senior ones at a smaller scale: a 2026 design posting for engineers with up to three years of experience, for example, asked for Verilog, digital design and familiarity with EDA tools[1]. A portfolio is evidence of those skills. For design roles it shows RTL that synthesizes cleanly and meets a timing target; for verification roles it shows a testbench that checks itself, measures coverage and has found real bugs; for implementation roles it shows a design taken through synthesis, timing and layout with the reports to prove it.
The project ladder in Learning Path by Role, from counters and a UART up to a pipelined processor taken through the full flow, gives a sequence that covers all three. Depth on a few projects is more convincing than many unfinished ones.
Presenting a Project
A reviewer typically has a few minutes. A project that is quick to check has:
- A short README: what the design does, its interfaces, and the results.
- The RTL and the testbench, with instructions to run the simulation.
- The evidence: the test result, a coverage summary, the synthesis area and the timing slack at a stated clock.
- A note of what does not work yet and what you would change, which shows engineering judgement.
Public repositories on GitHub or a similar service are the usual place to publish. ChipVerify Lab can push a project to GitHub directly from the browser. Before publishing, check that nothing belongs to an employer or university course that forbids sharing.
Quick Check
Q: What evidence should a verification project include besides the testbench code?
Show Answer
Instructions to run it, the test results, a coverage summary and, ideally, examples of bugs it found. The evidence lets a reviewer see that the testbench actually checks the design.
Taping Out a Real Chip
Shared multi-project wafer shuttles put many small designs on one set of masks, so each design costs a fraction of a full tape-out. Tiny Tapeout uses this model to fabricate small designs from students and hobbyists on open process design kits: its first 2026 SkyWater shuttle carried 289 designs and its first 2026 IHP shuttle 283[2][3]. For one 2026 shuttle, members of one IEEE division got free design area[4]. Designs are built with the open-source flow, so the tape-out also teaches the tools.
Where Is This Used?
These programmes change with the industry. Efabless, which ran the shuttles behind Tiny Tapeout and other community chips, shut down in early 2025[5]. ChipFoundry acquired its assets in September 2025 and restarted the SkyWater shuttle service, and Tiny Tapeout continued with ChipFoundry, IHP and GlobalFoundries shuttles[6][7]. Check a programme's current terms before planning around it.
Internships and University Work
Internships give experience on real projects and tools and are a common route to a first job. As one example, a third-party guide citing NXP reports about 790 internships at NXP in 2025, with around 60 percent converted to full-time offers[8]. Conversion rates vary by company and year. University research projects, final-year projects and course tape-outs serve the same purpose, and many universities have access to commercial tools through vendor academic programmes.
Government programmes also train engineers at scale. India's Chips to Startup programme reported about 67,000 people trained by January 2026, with commercial design tools provided to more than 300 institutions[9]. The Common Foundation for Chip Careers covers the skills these programmes teach.
Contributing to Open Source
Open-source hardware and EDA projects such as Yosys, Verilator and OpenROAD are developed in public repositories, and their issue trackers and pull requests are open to anyone. Fixing a bug, adding a test or improving documentation shows the ability to read a large code base and work with other engineers, which is particularly relevant for CAD and EDA roles. Open processor and peripheral designs offer the same opportunity for verification: writing tests for an existing open core and reporting what they find.
What the First Job Looks Like
Companies organize engineers into levels, and each level has competencies the engineer is expected to meet. New graduates start at the first level with tasks suited to it, often assisting a senior engineer: running and triaging regressions, fixing lint or timing issues on a block, writing tests from a plan. As they spend time on projects, they take ownership of pieces of work, and responsibilities grow with each level. Some engineers find these early tasks narrower than expected: one Indian startup founder said that many new graduates at large companies are given regression work rather than design[10]. A portfolio that shows depth in one area can help an engineer get more interesting work sooner. How Chip Teams Are Staffed covers how teams decide who does what.
Quick Check
Q: Why do multi-project wafer shuttles make student tape-outs possible?
Show Answer
Many designs share one set of masks and one wafer run, so each design pays only a small part of the cost of a full tape-out.
Summary
- A portfolio shows the skills entry postings ask for: RTL that synthesizes, self-checking testbenches, designs taken through the flow.
- Good projects are easy to check: a README, run instructions, results and known limitations.
- Shared shuttles such as Tiny Tapeout let students fabricate small designs; the programmes behind them change, so check current terms.
- Internships, university projects, training programmes and open-source contributions are other routes to experience.
- First jobs start with tasks suited to the first level, often assisting seniors, and ownership grows with experience.
Sources
- Microchip design engineer (VLSI) off-campus drive 2026, FreshersHunt.
- Tiny Tapeout SKY 26a, Tiny Tapeout.
- Tiny Tapeout IHP 26a, Tiny Tapeout.
- Tiny Tapeout news: IEEE members get free tapeout on TTSKY26b, Tiny Tapeout, May 2026.
- Tiny Tapeout hits trouble as Efabless shuts its doors, Hackster.io.
- ChipFoundry acquires Efabless assets, GlobeNewswire, September 2025.
- Tiny Tapeout sees industrial boost as it recovers from Efabless closure, eeNews Europe.
- NXP internship guide, Extern.
- Chips to Startup programme progress, Press Information Bureau, Government of India, January 2026.
- Young Indian chip engineers in MNCs get regression roles, not design work, Outlook Business.
