UPF Design Flow

15 min read | Intermediate Level

What You'll Learn

• Understand where UPF fits in the RTL-to-GDS design flow
• Learn how simulation, synthesis, and physical design tools use UPF
• Recognize the role of power intent specification in each design stage
• Identify the EDA tool ecosystem supporting UPF

UPF in the RTL-to-GDS Flow

The ASIC/SoC design flow transforms high-level RTL descriptions into physical silicon layouts through multiple stages. UPF integrates at each stage, ensuring power intent remains consistent from specification to implementation.

Traditional Design Flow (Without UPF)

Before UPF standardization, power management was handled differently at each stage:

┌─────────────────┐
│  RTL Design     │  → Power logic mixed with functional code
└────────┬────────┘
         ↓
┌─────────────────┐
│  Simulation     │  → Limited power-aware checking
└────────┬────────┘
         ↓
┌─────────────────┐
│  Synthesis      │  → Tool-specific power commands
└────────┬────────┘
         ↓
┌─────────────────┐
│  Place & Route  │  → Different power specs
└────────┬────────┘
         ↓
┌─────────────────┐
│  Signoff        │  → Manual power verification
└─────────────────┘

This approach led to inconsistencies, errors, and significant manual effort to verify power intent across tools.

Modern Flow with UPF

UPF provides a unified power specification used throughout the flow:

┌──────────────────┐
│  Architecture    │  → Define power domains, states
└────────┬─────────┘
         ↓
┌──────────────────┐     ┌──────────────────┐
│  RTL Design      │ ←→  │  UPF Creation    │  (Parallel development)
└────────┬─────────┘     └────────┬─────────┘
         │                        │
         └────────────┬───────────┘
                      ↓
         ┌────────────────────────┐
         │  RTL + UPF Combined    │  → Single source of truth
         └────────┬───────────────┘
                  ↓
         ┌────────────────────────┐
         │  Power-Aware           │  → UPF defines X-propagation,
         │  Simulation            │     state transitions
         └────────┬───────────────┘
                  ↓
         ┌────────────────────────┐
         │  Logic Synthesis       │  → UPF guides cell insertion
         │  with UPF              │     (isolation, retention, LS)
         └────────┬───────────────┘
                  ↓
         ┌────────────────────────┐
         │  Physical Design       │  → UPF defines domain layout,
         │  with UPF              │     power routing
         └────────┬───────────────┘
                  ↓
         ┌────────────────────────┐
         │  Power Analysis        │  → UPF provides state info
         │  & Signoff             │     for accurate estimation
         └────────────────────────┘

The same UPF file accompanies the design through all stages, ensuring consistency. Tools read UPF to understand power intent and implement appropriate power management logic.

Power Intent Specification Phase

UPF creation begins early in the design cycle, often in parallel with RTL development.

Architecture and Planning

During architecture, power architects define:

• Power Domain Boundaries: Which blocks can be independently controlled?
• Voltage Levels: Operating voltages for each domain
• Power States: Sleep modes, active modes, performance states
• Power Management Strategy: When to gate power, isolate signals, retain state
• Control Mechanisms: How software controls power states

These decisions translate directly into UPF commands:

# Architecture Decision: CPU and GPU are separate power domains
create_power_domain PD_CPU -elements {CPU_subsystem}
create_power_domain PD_GPU -elements {GPU_subsystem}

# Architecture Decision: CPU runs at 1.0V, GPU at 0.9V for efficiency
add_power_state VDD_CPU -state {ACTIVE 1.0}
add_power_state VDD_GPU -state {ACTIVE 0.9} -state {SLEEP 0.0}

# Architecture Decision: GPU can be power-gated to save leakage
create_power_switch PSW_GPU -domain PD_GPU ...

Starting UPF early enables power-aware RTL simulation before physical design, catching power management bugs when they're easiest to fix.

UPF in Simulation and Verification

RTL simulation with UPF enables early detection of power management issues.

Power-Aware Simulation

Simulators use UPF to:

• Corrupt Signal Values: Propagate 'X' from powered-off domains
• Check Isolation: Verify isolation cells prevent X-propagation
• Check Retention: Ensure state is preserved during power-down
• Verify Level Shifting: Validate voltage domain crossings
• Simulate Power States: Test state machine transitions

Example UPF for simulation:

# Define isolation strategy
set_isolation ISO_GPU -domain PD_GPU \
  -isolation_signal iso_gpu \
  -isolation_sense high \
  -clamp_value 0

# Define retention strategy
set_retention RET_GPU -domain PD_GPU \
  -retention_signal ret_gpu \
  -retention_sense high

During simulation, when PD_GPU powers down:

1. Simulator forces all GPU outputs to 'X'
2. If iso_gpu is asserted, isolation cells clamp outputs to 0 (preventing X-propagation)
3. If ret_gpu is asserted, retention registers preserve their state
4. Testbench can verify correct power sequencing

# UPF tells synthesis WHERE to insert isolation
set_isolation ISO_CPU_TO_TOP -domain PD_CPU \
  -isolation_supply_set SS_TOP \    # Use always-on supply
  -isolation_signal iso_cpu_en \
  -isolation_sense high \
  -clamp_value 0 \
  -location parent                   # Insert in parent domain

# UPF specifies level shifter locations
set_level_shifter LS_GPU -domain PD_GPU \
  -applies_to outputs \
  -location self                     # Insert at domain boundary

# Map isolation strategy to specific library cell
map_isolation_cell ISO_CPU_TO_TOP \
  -domain PD_CPU \
  -lib_cells {ISOL_AND_0}            # Use AND-based isolation, clamp to 0

# Map level shifter to library cell
map_level_shifter_cell LS_GPU \
  -domain PD_GPU \
  -lib_cells {LS_HL}                 # High-to-low level shifter

# UPF: Define power switch
create_power_switch PSW_CPU -domain PD_CPU \
  -input_supply_port {vin VDD} \          # Input from always-on
  -output_supply_port {vout VDD_CPU} \    # Output to domain
  -control_port {ctrl pwr_enable_cpu} \
  -on_state {on vin {ctrl}} \
  -off_state {off {!ctrl}}

# Physical design tool:
# 1. Places switch cells near PD_CPU
# 2. Routes VDD to switch input
# 3. Routes switch output to VDD_CPU power grid
# 4. Connects pwr_enable_cpu control signal

# Define power states
add_pst_state PST_SYSTEM \
  -state {ACTIVE   {VDD_CPU ON}  {VDD_GPU ON}}  \
  -state {GPU_IDLE {VDD_CPU ON}  {VDD_GPU OFF}} \
  -state {SLEEP    {VDD_CPU OFF} {VDD_GPU OFF}}

# Power analysis tool:
# - Estimates power for each state
# - Reports: ACTIVE=500mW, GPU_IDLE=200mW, SLEEP=5mW
# - Calculates average power based on state probabilities

1. RTL Simulation
   UPF Info Used: Isolation/retention strategies, power states
   Tool Actions:
   - Propagates 'X' from powered-off domains
   - Checks isolation prevents X-propagation
   - Verifies retention preserves state
   - Validates power state transitions

2. Logic Synthesis
   UPF Info Used: Domain boundaries, isolation/retention/LS specs
   Tool Actions:
   - Inserts isolation cells at domain outputs
   - Replaces flip-flops with retention variants
   - Inserts level shifters at voltage crossings
   - Maps strategies to library cells

3. Place & Route
   UPF Info Used: Power switches, supply networks, domain boundaries
   Tool Actions:
   - Creates separate power domains (floorplan)
   - Places power switch cells
   - Routes domain-specific VDD nets
   - Implements power grid per domain

4. Power Analysis
   UPF Info Used: Power states, supply voltages, domain structure
   Tool Actions:
   - Estimates power per domain
   - Calculates state-dependent power
   - Reports power for each PST state
   - Validates power budget compliance