UPF Advanced Level Shifters

Conservative practice: Set threshold to 0.0V (insert shifters for any voltage difference) or very low value (0.05V). Small voltage differences can still cause reliability and timing issues. Only use higher thresholds if process characterization proves it's safe.

Advanced Library Cell Mapping

Mapping level shifters to library cells with drive strength and voltage range selection.

Multi-Cell Mapping

# Provide multiple cell options with different drive strengths
map_level_shifter_cell LS_CPU_OUT -domain PD_CPU \
  -lib_cells {
    LS_LH_1V0_1V2_X1    # Low drive (small loads)
    LS_LH_1V0_1V2_X2    # Medium drive
    LS_LH_1V0_1V2_X4    # High drive (high fanout)
    LS_LH_1V0_1V2_X8    # Very high drive
  }

Synthesis tools select appropriate drive strength based on:

• Fanout (number of sinks)
• Capacitive load
• Timing requirements
• Power budget

Voltage-Specific Cell Mapping

# Different cells for different voltage transitions
map_level_shifter_cell LS_CPU_OUT -domain PD_CPU \
  -lib_cells {LS_LH_1V0_1V2_X1 LS_LH_1V0_1V2_X2}

map_level_shifter_cell LS_IO_OUT -domain PD_IO \
  -lib_cells {LS_HL_1V8_1V2_X1 LS_HL_1V8_1V2_X2}

Each voltage combination (1.0V→1.2V, 1.8V→1.2V) uses appropriate library cells designed for that range.

Handling Bidirectional Signals

Bidirectional signals (inout ports) require special level shifter handling.

Bidirectional Challenge

Domain A (1.0V)    Bidirectional Bus    Domain B (1.2V)
┌────────────┐     ←─────────────→      ┌────────────┐
│            │                          │            │
│  Logic ────┼──────[LS both ways?]────┼──── Logic  │
│            │                          │            │
└────────────┘                          └────────────┘

Problem: Single wire must support voltage translation in both directions.

Solution 1: Separate Directional Signals

Convert bidirectional to separate input/output with control:

# Wrapper converts bidir to input + output + direction control
# Then apply normal level shifters to each direction

set_level_shifter LS_BUS_OUT -domain PD_CPU \
  -applies_to outputs \
  -location self

set_level_shifter LS_BUS_IN -domain PD_CPU \
  -applies_to inputs \
  -location parent

Solution 2: Bidirectional Level Shifter Cells

# Use special bidirectional level shifter cells (if available)
map_level_shifter_cell LS_BIDIR -domain PD_CPU \
  -lib_cells {LS_BIDIR_1V0_1V2_X1 LS_BIDIR_1V0_1V2_X2}

Bidirectional level shifter cells contain:

• Two level shifters (one per direction)
• Direction control logic
• Tri-state buffers for bus control

Bidirectional level shifter cells are complex and not available in all libraries. When possible, redesign interfaces to avoid true bidirectional signals at voltage boundaries, using separate input/output paths with direction control instead.

Level Shifter Optimization Techniques

1. Cluster Shifters for Related Signals

# Group related signals (e.g., data bus) for efficient placement
set_level_shifter LS_DATA_BUS -domain PD_MEM \
  -applies_to outputs \
  -location self \
  -elements {mem_inst/data_out[*]}  # All data bus bits together

Benefits: Better routing, reduced area, consistent timing across bus.

2. Minimize Shifter Count on Critical Paths

BAD (Multiple Shifters):
CPU (1.0V) → [LS] → MEM (1.2V) → [LS] → IO (1.8V)
Total delay: 2× shifter delay

GOOD (Single Shifter):
CPU (1.0V) → MEM (1.0V) → [LS] → IO (1.8V)
Total delay: 1× shifter delay (50% reduction)

Design tip: Keep critical path blocks at same voltage to minimize level shifter overhead.

3. Use Lower-Delay Cells for Critical Paths

# Map critical path to fast level shifter cells
map_level_shifter_cell LS_CRITICAL -domain PD_CPU \
  -lib_cells {LS_LH_FAST_1V0_1V2}  # Fast but higher power variant

Some libraries offer low-delay level shifters (higher power, larger area) for timing-critical signals.

Complete Advanced Example

# ===================================================================
# Advanced Level Shifter Configuration
# ===================================================================

# Domain structure
create_power_domain PD_TOP -include_scope
create_power_domain PD_CPU -elements {cpu_inst}
create_power_domain PD_MEM -elements {mem_ctrl}
create_power_domain PD_IO -elements {io_pads}

# Supply definitions (voltages: TOP=1.2V, CPU=1.0V, MEM=1.0V, IO=1.8V)
# ... (supply nets, sets, states omitted for brevity)

# CPU Level Shifters (1.0V ↔ 1.2V)
# Critical path: Use self placement for timing control
set_level_shifter LS_CPU_CRITICAL -domain PD_CPU \
  -applies_to outputs \
  -location self \
  -rule low_to_high \
  -elements {cpu_inst/critical_path/*}

# Non-critical CPU outputs: Automatic placement
set_level_shifter LS_CPU_GENERAL -domain PD_CPU \
  -applies_to outputs \
  -location automatic \
  -threshold 0.05

# CPU inputs: Parent placement
set_level_shifter LS_CPU_IN -domain PD_CPU \
  -applies_to inputs \
  -location parent

# MEM stays at 1.0V (same as CPU) - no shifters needed between CPU-MEM

# IO Level Shifters (1.8V ↔ 1.2V)
# High-voltage interface requires specific cells
set_level_shifter LS_IO_OUT -domain PD_IO \
  -applies_to outputs \
  -location self \
  -rule high_to_low

set_level_shifter LS_IO_IN -domain PD_IO \
  -applies_to inputs \
  -location parent \
  -rule low_to_high

# Library Cell Mapping
# Critical path: Multiple drive strengths + fast variant
map_level_shifter_cell LS_CPU_CRITICAL -domain PD_CPU \
  -lib_cells {
    LS_LH_FAST_1V0_1V2_X2
    LS_LH_FAST_1V0_1V2_X4
    LS_LH_FAST_1V0_1V2_X8
  }

# General paths: Standard cells
map_level_shifter_cell LS_CPU_GENERAL -domain PD_CPU \
  -lib_cells {
    LS_LH_1V0_1V2_X1
    LS_LH_1V0_1V2_X2
    LS_LH_1V0_1V2_X4
  }

map_level_shifter_cell LS_CPU_IN -domain PD_CPU \
  -lib_cells {LS_HL_1V2_1V0_X1 LS_HL_1V2_1V0_X2}

# IO cells: High-voltage range
map_level_shifter_cell LS_IO_OUT -domain PD_IO \
  -lib_cells {LS_HL_1V8_1V2_X1 LS_HL_1V8_1V2_X2 LS_HL_1V8_1V2_X4}

map_level_shifter_cell LS_IO_IN -domain PD_IO \
  -lib_cells {LS_LH_1V2_1V8_X1 LS_LH_1V2_1V8_X2}

# ===================================================================
# Strategy Summary:
# - Critical paths: Explicit control with fast cells
# - General paths: Automatic insertion with standard cells
# - CPU-MEM: Same voltage, no shifters (optimized)
# - Voltage-specific cell mapping for each transition
# ===================================================================

Common Beginner Mistakes

# SUBOPTIMAL: Only one drive strength
map_level_shifter_cell LS_CPU -domain PD_CPU \
  -lib_cells {LS_LH_1V0_1V2_X1}

# BETTER: Multiple options for synthesis optimization
map_level_shifter_cell LS_CPU -domain PD_CPU \
  -lib_cells {
    LS_LH_1V0_1V2_X1
    LS_LH_1V0_1V2_X2
    LS_LH_1V0_1V2_X4
  }

# INCOMPLETE: Only output shifters
set_level_shifter LS_CPU_OUT -domain PD_CPU \
  -applies_to outputs \
  -location self

# COMPLETE: Both directions
set_level_shifter LS_CPU_OUT -domain PD_CPU \
  -applies_to outputs \
  -location self

set_level_shifter LS_CPU_IN -domain PD_CPU \
  -applies_to inputs \
  -location parent

# ===================================================================
# Optimized Level Shifter Strategy
# ===================================================================

# OPTION 1: Run critical domains at same voltage (Best for timing)
# Change CACHE to 1.2V (same as CORE) - eliminates shifters on critical path
# This is the preferred solution for zero shifter delay on critical path

# OPTION 2: If CACHE must stay at 1.0V for power reasons:

# CACHE outputs to CORE (critical path)
# Place shifters in CACHE domain (has 500ps slack, can absorb LS delay)
set_level_shifter LS_CACHE_TO_CORE -domain PD_CACHE \
  -applies_to outputs \
  -location self \              # In CACHE domain (has slack)
  -rule low_to_high \
  -elements {cache_inst/critical_out[*]}

# CACHE inputs from CORE
# Place shifters in CACHE domain to keep CORE critical path clean
set_level_shifter LS_CORE_TO_CACHE -domain PD_CACHE \
  -applies_to inputs \
  -location self \              # In CACHE domain
  -rule high_to_low

# CACHE to PERIPH (non-critical, 2ns slack)
# Use automatic insertion for simplicity
set_level_shifter LS_CACHE_PERIPH -domain PD_CACHE \
  -applies_to both \
  -location automatic \
  -threshold 0.05

set_level_shifter LS_PERIPH_CACHE -domain PD_PERIPH \
  -applies_to both \
  -location automatic \
  -threshold 0.05

# Cell Mapping
# Critical path: Fast, multiple drive strengths
map_level_shifter_cell LS_CACHE_TO_CORE -domain PD_CACHE \
  -lib_cells {
    LS_LH_FAST_1V0_1V2_X2
    LS_LH_FAST_1V0_1V2_X4
  }

map_level_shifter_cell LS_CORE_TO_CACHE -domain PD_CACHE \
  -lib_cells {
    LS_HL_FAST_1V2_1V0_X2
    LS_HL_FAST_1V2_1V0_X4
  }

# Non-critical: Standard cells, smaller drive
map_level_shifter_cell LS_CACHE_PERIPH -domain PD_CACHE \
  -lib_cells {LS_LH_1V0_0V9_X1 LS_LH_1V0_0V9_X2}

map_level_shifter_cell LS_PERIPH_CACHE -domain PD_PERIPH \
  -lib_cells {LS_LH_0V9_1V0_X1 LS_LH_0V9_1V0_X2}

# ===================================================================
# Key Optimizations:
# 1. Critical path shifters in CACHE (has slack) not CORE (0 slack)
# 2. Use FAST level shifter cells for critical signals
# 3. Automatic insertion for non-critical (less UPF maintenance)
# 4. Optimal solution: Run CORE and CACHE at same 1.2V (zero LS delay)
# ===================================================================