UPF Power Optimization

Power optimization is iterative, not one-time. Each technique interacts with others—clock gating affects timing, multi-Vt affects area, DVFS affects power domains. Expect 3-5 optimization iterations to converge on the optimal solution.

Clock Gating

Clock Power Contribution

Clock networks typically consume 30-40% of total dynamic power in SoCs due to:

• High activity factor (toggles every cycle)
• High fanout (drives thousands of flip-flops)
• Large capacitance (long wires, buffers)

Automatic Clock Gating Insertion

# Design Compiler clock gating flow
compile_ultra -gate_clock \
              -gate_clock_style latch \      # Latch-based gating (safer)
              -clock_gating_min_bitwidth 4   # Gate registers =4 bits

# Report clock gating results
report_clock_gating -verbose

# Output:
# Register banks with clock gating:
#   cpu_regs[31:0]: 32 FFs gated (saves 4.2mW)
#   pipeline_stage1[63:0]: 64 FFs gated (saves 7.8mW)
#   cache_tag_array[127:0]: 128 FFs gated (saves 12.3mW)
# Total dynamic power reduction: 35%

Manual Clock Gating for FSMs

// Before: FSM clock always active
always_ff @(posedge clk)
  if (rst_n) state <= next_state;

// After: Clock gating based on activity
logic fsm_enable;
assign fsm_enable = (state != IDLE) || (start_req);

always_ff @(posedge clk)
  if (rst_n && fsm_enable) state <= next_state;

// Synthesis inserts clock gating cell:
// ICG (Integrated Clock Gate) between clk and FSM flip-flops

Clock gating is the highest ROI power optimization, typically achieving 30-40% dynamic power reduction with minimal area overhead (< 1%) and no performance impact.

Operand Isolation

Unnecessary Switching Problem

Functional units consume power even when their outputs are discarded:

// ALU always operates, even when result unused
always_comb begin
  alu_result = operand_a + operand_b;  // Always computes
  if (alu_enable)
    output_reg <= alu_result;  // Only used when enabled
  else
    output_reg <= output_reg;  // Result discarded!
end

// Problem: ALU toggles on every cycle, wasting power

Operand Isolation Implementation

// Isolate ALU operands when disabled
logic [31:0] alu_a_gated, alu_b_gated;

assign alu_a_gated = alu_enable ? operand_a : 32'b0;
assign alu_b_gated = alu_enable ? operand_b : 32'b0;

always_comb begin
  alu_result = alu_a_gated + alu_b_gated;  // No switching when disabled
  if (alu_enable)
    output_reg <= alu_result;
  else
    output_reg <= output_reg;
end

// Power savings: 60-80% when ALU disabled (typical utilization: 30%)
// Net savings: ~20% of ALU power

Memory Power Management

SRAM Power Modes

SRAM arrays support multiple power modes:

Cache Power Management Example

// L2 cache with power management
module l2_cache (
  input logic [31:0] addr,
  input logic rd_req, wr_req,
  input logic [1:0] power_mode,  // 00=Active, 01=Idle, 10=Drowsy, 11=Off
  output logic [127:0] data_out
);

  // SRAM banks (4 x 64KB)
  sram_bank bank0 (.power_mode(bank0_mode), ...);
  sram_bank bank1 (.power_mode(bank1_mode), ...);
  sram_bank bank2 (.power_mode(bank2_mode), ...);
  sram_bank bank3 (.power_mode(bank3_mode), ...);

  // Bank-level power management
  always_comb begin
    // Active bank for current access
    active_bank = addr[17:16];

    // Put inactive banks in Drowsy mode
    bank0_mode = (active_bank == 0) ? power_mode : 2'b10;  // Drowsy
    bank1_mode = (active_bank == 1) ? power_mode : 2'b10;
    bank2_mode = (active_bank == 2) ? power_mode : 2'b10;
    bank3_mode = (active_bank == 3) ? power_mode : 2'b10;
  end

  // Power savings: 75% when 1/4 banks active
endmodule

Dynamic Voltage-Frequency Scaling (DVFS)

DVFS Operating Points

DVFS trades performance for power by reducing voltage and frequency:

Power scales with V²f: Halving frequency and voltage reduces power by 75%

DVFS Controller Implementation

// DVFS controller monitors workload and adjusts voltage/frequency
module dvfs_controller (
  input logic [31:0] cpu_utilization,  // 0-100%
  input logic [31:0] temp_sensor,      // Die temperature
  output logic [1:0] operating_point   // 00=Low, 01=Eco, 10=Normal, 11=Turbo
);

  always_comb begin
    // High utilization + low temp: Turbo mode
    if (cpu_utilization > 80 && temp_sensor < 85)
      operating_point = 2'b11;  // Turbo

    // High utilization + high temp: Normal mode (thermal limit)
    else if (cpu_utilization > 60)
      operating_point = 2'b10;  // Normal

    // Medium utilization: Eco mode
    else if (cpu_utilization > 30)
      operating_point = 2'b01;  // Eco

    // Low utilization: Low power mode
    else
      operating_point = 2'b00;  // Low
  end
endmodule

Power Optimization Workflow

1. BASELINE: Measure initial power (P0)
   - Run power analysis on unoptimized design
   - Identify power hotspots (which modules consume most)

2. CLOCK GATING: 30-40% dynamic power reduction
   - Enable automatic clock gating in synthesis
   - Manually gate FSMs and low-activity blocks
   - Measure: P1 = P0 × 0.65

3. MULTI-VT: 40-50% leakage reduction
   - Configure multi-Vt constraints (10% LVT, 60% HVT)
   - Re-synthesize with power optimization
   - Measure: P2 = P1 × 0.70 (leakage) + P1 × 1.0 (dynamic)

4. OPERAND ISOLATION: 5-15% dynamic reduction
   - Identify low-utilization functional units
   - Add operand gating when units disabled
   - Measure: P3 = P2 × 0.92

5. MEMORY OPTIMIZATION: 10-20% reduction
   - Enable SRAM power modes (Idle/Drowsy)
   - Implement bank-level power management
   - Measure: P4 = P3 × 0.85

6. DVFS: Runtime power-performance trade-off
   - Define operating points (voltage-frequency pairs)
   - Implement DVFS controller
   - Measure: P5 = P4 × (0.3 to 1.0) depending on workload

Total power reduction: 70-85% from baseline

Common Beginner Mistakes