UPF Library Cells for Low Power

Using incorrect library cells—or cells not designed for power management—causes functional failures in silicon. Isolation cells without always-on supply capability allow X-propagation. Retention cells without proper power domains lose state. Level shifters without correct voltage tolerance cause signal corruption.

Isolation Cells

Isolation Cell Purpose

When a domain powers down, its outputs become X (unknown). Isolation cells prevent this X-propagation by clamping signals to known values (0 or 1) using an always-on supply.

Isolation Cell Types

Isolation Cell Structure

// ISO_AND cell schematic
module ISO_AND (
  input  A,      // Data input (from powered-down domain)
  input  EN,     // Isolation enable (always-on supply)
  output Z       // Isolated output (to always-on domain)
);
  // Powered by always-on supply (VDD_AON)
  // When EN=0: Z=0 (isolated/clamped)
  // When EN=1: Z=A (pass-through)

  assign Z = A & EN;
endmodule

// ISO_OR cell schematic
module ISO_OR (
  input  A,
  input  EN,
  output Z
);
  // When EN=0: Z=1 (isolated/clamped)
  // When EN=1: Z=A (pass-through)

  assign Z = A | ~EN;
endmodule

Selection Criteria

• Clamp value: Match signal semantics (0 for active-low, 1 for active-high)
• Drive strength: Match fanout load (X1, X2, X4, X8)
• Area: Minimize for non-critical paths
• Supply pins: Ensure cell supports always-on supply connection

Retention Flip-Flops

Retention Cell Architecture

Retention flip-flops extend standard flip-flops with shadow latches powered by always-on retention supply:

Standard Flip-Flop:
  [D] --> [Master Latch] --> [Slave Latch] --> [Q]
          Powered by VDD (switchable)

Retention Flip-Flop:
  [D] --> [Master Latch] --> [Slave Latch] --> [Q]
          Powered by VDD (switchable)
                 |
                 v
          [Shadow Latch] --> (retention storage)
          Powered by VDD_RET (always-on)

SAVE operation: Copy Slave Latch --> Shadow Latch
RESTORE operation: Copy Shadow Latch --> Slave Latch

Retention Cell Interface

// Retention flip-flop (DFFR)
module DFFR_X1 (
  input  D,           // Data input
  input  CK,          // Clock
  input  RN,          // Active-low reset
  input  SAVE,        // Save trigger (capture to shadow latch)
  input  RESTORE,     // Restore trigger (restore from shadow)
  output Q,           // Data output

  // Power pins
  input  VDD,         // Primary supply (switchable)
  input  VDD_RET,     // Retention supply (always-on, typically 0.6V)
  input  VSS          // Ground
);

  // Internal: master/slave latches (VDD powered)
  // Internal: shadow latch (VDD_RET powered)

  // Normal operation: Q follows D on CK rising edge
  // SAVE=1: Shadow latch captures current Q value
  // VDD powers down: Shadow latch retains value
  // VDD powers up: Q is X until...
  // RESTORE=1: Q restored from shadow latch
endmodule

Timing Requirements

SAVE timing:
  SAVE pulse width: = 3-5 clock cycles (ensure all FFs capture)
  SAVE to power-down: = 10 clock cycles (allow propagation)

RESTORE timing:
  Power-up to RESTORE: = 20 clock cycles (allow supply stabilization)
  RESTORE pulse width: = 3-5 clock cycles (ensure all FFs restore)

Level Shifters

Level Shifter Types

Different voltage transitions require different level shifter architectures:

High-to-Low Level Shifter (LS_HL)

// LS_HL: 1.0V input to 0.8V output
module LS_HL_X1 (
  input  A,      // Input (high voltage domain, e.g., 1.0V)
  output Z,      // Output (low voltage domain, e.g., 0.8V)

  input  VDDH,   // High voltage supply (1.0V)
  input  VDDL,   // Low voltage supply (0.8V)
  input  VSS
);

  // Simple buffer architecture works because:
  // - 1.0V logic-high easily recognized as high by 0.8V domain
  // - 0V logic-low is 0V in both domains

  // BUT: Input protection needed to prevent PMOS gate oxide stress
endmodule

Low-to-High Level Shifter (LS_LH)

// LS_LH: 0.8V input to 1.0V output
module LS_LH_X1 (
  input  A,      // Input (low voltage domain, e.g., 0.8V)
  output Z,      // Output (high voltage domain, e.g., 1.0V)

  input  VDDL,   // Low voltage supply (0.8V)
  input  VDDH,   // High voltage supply (1.0V)
  input  VSS
);

  // More complex: cross-coupled PMOS pull-up
  // Required because 0.8V input insufficient to fully switch
  // NMOS transistors in 1.0V domain

  // Slower than LS_HL due to cross-coupled feedback settling
endmodule

Multi-Vt Cell Variants

Threshold Voltage Trade-offs

Modern libraries provide three Vt variants for each cell:

Leakage Power Comparison

Example: NAND2 gate in 7nm process

NAND2_LVT:
  Delay: 15ps
  Leakage: 12nA
  Area: 0.45 um²

NAND2_RVT:
  Delay: 20ps (+33%)
  Leakage: 3nA (-75%)
  Area: 0.48 um² (+7%)

NAND2_HVT:
  Delay: 28ps (+87%)
  Leakage: 0.8nA (-93%)
  Area: 0.52 um² (+16%)

Optimal mix: 10% LVT, 30% RVT, 60% HVT
  Timing: Meets all constraints
  Leakage: 45% reduction vs. all-LVT
  Area: +2.3%

Multi-Vt optimization is the single most effective leakage reduction technique, typically achieving 40-50% savings with minimal area/timing impact. Always specify multi-Vt constraints in synthesis.

Common Beginner Mistakes

// WRONG: Using LS_HL for low-to-high transition
// 0.8V domain drives 1.0V domain with LS_HL cell
LS_HL ls_wrong (.A(signal_08v), .Z(signal_10v));
// Result: Insufficient voltage swing, signal corruption

// CORRECT: Use LS_LH for low-to-high
LS_LH ls_correct (.A(signal_08v), .Z(signal_10v));