Verilog is a text-based language used to describe, simulate and synthesize digital circuits. This page explains what Verilog is, where it came from, how it differs from software languages, and how this tutorial is organized, so that you know what to expect before you write your first line of code.
12 min read | Beginner Level
What You'll Learn
- Understand what Verilog is and how it revolutionized digital circuit design
- Learn the key differences between Verilog and software programming languages
- Master the concept of hardware abstraction and behavioral modeling
- Write your first Verilog module with proper syntax and structure
What is Verilog ?
Verilog is a hardware description language (HDL): a language for describing digital systems such as gates, flip-flops, counters, processors and complete chips as text. It was created in 1983 and 1984 at Gateway Design Automation as a language for its logic simulator. Cadence acquired Gateway around 1990 and soon after made the language public, and it was standardized as IEEE 1364 in 1995, with revisions in 2001 and 2005. In 2009 it was merged into the SystemVerilog standard, IEEE 1800, which still contains all of Verilog.
Verilog is used to design both ASICs (custom chips) and FPGAs (programmable chips). The same code serves two purposes:
- Simulation: a simulator runs the code to check that the circuit behaves as intended
- Synthesis: a synthesis tool converts the code into a netlist of real gates and flip-flops
Verilog supports several levels of description. You can describe a circuit structurally by connecting gates and smaller blocks, at the register transfer level (RTL) by describing how data moves between registers on each clock edge, or behaviorally by describing what the circuit does. Large designs are built hierarchically: small modules such as adders and flip-flops are combined into bigger blocks, which are combined into a complete chip. You can read more about these levels in Design Abstraction Layers.
Real-World Application
Processors, graphics chips, network switches, storage controllers and the chips inside phones, cars and home appliances are designed with Verilog or its successor SystemVerilog. A typical chip project has hundreds of thousands of lines of RTL code, written by many engineers as separate modules and then connected into one design. The same language is used for small FPGA projects such as a motor controller or a video interface on a hobby board.
What was used before Verilog ?
Before HDLs became common, digital circuits were designed with schematic capture: engineers drew gates, flip-flops and wires in a drawing tool, and that drawing was the design. This works for a few hundred gates, but it becomes slow and error-prone for thousands or millions of gates, and every change means redrawing part of the circuit. For small programmable logic devices, simple languages such as ABEL described logic as Boolean equations, but they could not describe large designs.
The other major HDL, VHDL, was developed at about the same time as Verilog. It came out of the U.S. Department of Defense VHSIC (Very High Speed Integrated Circuit) program in the early 1980s and was standardized as IEEE 1076 in 1987. VHDL is strongly typed and more verbose than Verilog. It is still widely used, especially in Europe and in defense and aerospace projects, and many companies use both languages. The VHDL code below describes a 2-input AND gate.
-- and_gate.vhdl
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Entity declaration: defines the inputs and outputs
entity and_gate is
Port (
A : in STD_LOGIC;
B : in STD_LOGIC;
Y : out STD_LOGIC
);
end and_gate;
-- Architecture: describes the behavior or structure
architecture Behavioral of and_gate is
begin
Y <= A and B;
end Behavioral;
For comparison, the same AND gate in Verilog:
// and_gate.v
module and_gate (input A, B, output Y);
assign Y = A & B;
endmodule
Both descriptions synthesize to exactly the same hardware, a single 2-input AND gate. The difference is only in how much text each language needs.
Why is Verilog better than its predecessor languages ?
Compared with schematics and simple equation languages, and in some respects compared with VHDL, Verilog offers:
- Simpler syntax: Verilog's syntax is compact and looks similar to C, so it is quick to learn and to write. This is one reason it is popular in industry, although VHDL's stricter typing catches some mistakes earlier
- Behavioral modeling: the same language covers everything from individual gates and transistor switches to high-level behavior, so complex functions can be described in a few lines
- Abstraction: modules and ports let designers build and reuse blocks and work at a higher level, which speeds up design
- Tool support: because Verilog is so widely used, almost every simulator, synthesis tool, FPGA tool and lint checker supports it, including free and open-source ones
How is Verilog useful ?
Verilog provides an abstraction layer that hides how a design is implemented and which technology it is built in. Imagine designing a positive-edge triggered D flip-flop by hand. You would need to know the arrangement of its transistors, its timing values such as rise time, fall time and clock-to-Q delay, and its power, drive strength and other physical properties.
With Verilog, you can focus on the behavior of the circuit and leave the physical details to tools later in the design flow. The same code can be built in different chip technologies or on different FPGAs without changes.
Verilog Code Example
The example below describes the behavior of a 3-bit up/down counter. It counts up when up_down is 1 and down when up_down is 0. When the reset rstn is 0, the counter is cleared to 0, so the reset is active-low.
module ctr (input up_down,
clk,
rstn,
output reg [2:0] out);
always @ (posedge clk)
if (!rstn)
out <= 0;
else begin
if (up_down)
out <= out + 1;
else
out <= out - 1;
end
endmodule
The code does not mention a single NAND or NOR gate, yet it is clear how the counter works. Because out is 3 bits wide, it counts from 0 to 7 and then wraps back to 0 when counting up, and from 0 back to 7 when counting down. The physical implementation can use any of many flip-flop designs optimized for area, power or speed. These are provided in standard cell libraries, and the tools pick from them later in the flow.
Synthesis result: Three D flip-flops hold out. Their next value comes from an incrementer (out + 1) and a decrementer (out - 1), selected by a 2-to-1 multiplexer controlled by up_down; tools often merge the two into one adder that adds +1 or -1. An AND gate per bit forces the next value to 0 when rstn is 0. Because the reset is only checked inside always @ (posedge clk), it is a synchronous reset.
Hardware Abstraction: You don't specify transistors or gate connections. You describe what the circuit should do, and synthesis tools decide how to build it in silicon.
Quick Check
The counter holds out = 3'd0, reset is inactive and up_down is 0. What is out after the next rising clock edge?
Show Answer
3'd7 (3'b111). Counting down from 0 wraps around, because a 3-bit value can only hold 0 to 7. In hardware, the decrementer simply produces 111 and the upper bits that would hold the borrow do not exist.
How is Verilog different from software languages like C and Java ?
Verilog is used to describe digital circuits and systems, while C and Java are used to write programs that run on general-purpose computers. Even though Verilog borrows some syntax from C, such as operators and if statements, the two are used very differently:
- Purpose: Verilog designs hardware; C and Java create software
- Building blocks: Verilog has wires, registers and modules; C and Java have variables, functions and classes
- Execution: Verilog is synthesized into gates on a chip or an FPGA configuration; C and Java are compiled into instructions that a processor executes one after another
- Testing: Verilog is tested by running it in a hardware simulator with a testbench; software is tested by running the program itself
- Reuse: a Verilog module is reused by instantiating it, which creates another copy of the hardware; software reuses code by calling the same function again
The biggest difference is parallelism. In software, line 2 runs after line 1. In hardware, every gate and flip-flop works at the same time, all the time. Verilog is therefore a specialized language for describing hardware, not a general-purpose programming language, even though it shares some syntax and ideas with C.
Hardware Accelerators
When a task such as video encoding, encryption or neural network inference is too slow in software, engineers move it into dedicated hardware. A software loop that processes 64 values one at a time can become 64 hardware units that process all values in the same clock cycle. This is only possible because hardware runs in parallel, and it is why the same task can be many times faster and use much less energy in a custom circuit.
What may replace Verilog in the future ?
It is hard to predict what will replace Verilog, but several technologies are already changing how digital systems are designed and verified:
- High-Level Synthesis (HLS): tools generate hardware automatically from C, C++ or SystemC code. Designers work at a higher level instead of describing every register transfer, which can make design faster and allow more design options to be explored. HLS is common for algorithm-heavy blocks such as signal and image processing
- AI and machine learning: AI-based tools help write and review RTL, generate tests and optimize the physical implementation, reducing manual effort
- Newer HDLs: languages such as Chisel (based on Scala) and MyHDL or Amaranth (based on Python) bring modern programming ideas and higher-level abstractions, and they usually generate Verilog as their output
Even with these tools, the output is usually Verilog, and engineers still need to read, debug and verify it. Understanding Verilog remains essential.
Verilog vs SystemVerilog: Verilog remains the foundation, but most chip teams today write SystemVerilog, which extends Verilog with stronger verification features, object-oriented programming and richer data types. Everything you learn in this tutorial carries over directly to SystemVerilog.
Verilog vs Software Languages - Quick Comparison
| Aspect | Verilog | C / Java |
|---|---|---|
| Purpose | Describes hardware circuits | Writes software programs |
| Execution | Synthesized into gates on a chip or configured onto an FPGA | Compiled and executed on a processor |
| Concurrency | All blocks run in parallel | Instructions run one after another (unless threads are used) |
| Time | Built-in delays, clocks and simulation time | No built-in concept of time |
| Data types | Model physical wires and storage, with bit widths and 4 values (0, 1, x, z) | Model abstract values in memory (int, float, objects) |
Common Beginner Mistakes
Mistake #1: Assuming sequential execution
Wrong: Expecting b to equal d right after one clock edge, because a is "assigned first"
always @ (posedge clk) a <= d;
always @ (posedge clk) b <= a;
Right: Each always block is separate hardware that runs in parallel. At each clock edge, b receives the value a had before the edge, so b is one clock cycle behind a
Why? In software, a = 1; b = a; runs line by line. In hardware, the two blocks above are two flip-flops connected in series, a 2-stage shift register. For sequential logic, use clocked always @ (posedge clk) blocks with non-blocking assignments (<=), and think in terms of what each flip-flop holds after the edge.
Mistake #2: Expecting wires to store values
Wrong:
wire [3:0] count;
always @ (posedge clk)
count <= count + 1; // Compile error: a wire cannot be assigned in an always block
Right: reg [3:0] count;
Why? A wire is only a connection: it shows whatever value drives it, and if nothing drives it, its value is z (floating). Values assigned in always or initial blocks must be held in a reg. Use wires for connections between modules and assign statements, and reg for values assigned procedurally.
Mistake #3: Treating for loops like software loops that run over time
Wrong: Expecting this loop to take 8 clock cycles to count the 1s in data
integer i;
always @ (*) begin
ones = 0;
for (i = 0; i < 8; i = i + 1)
ones = ones + data[i];
end
Right: In synthesizable code, a loop is unrolled: the tool creates 8 copies of the adder, and the result is ready in the same clock cycle
Why? A loop in hardware describes replicated logic, not repetition over time. A loop with 100 iterations can create 100 copies of the circuit, which costs area and can make the logic path too long for the clock. Use loops for repetitive wiring or bit-level operations, and use a counter with a clock when you really want something to happen over several cycles.
Practice Exercise
Challenge: Trace the Up/Down Counter
The ctr module is reset so that out = 0, then rstn goes to 1. For the next 8 rising clock edges, up_down is 1 for the first 3 edges and 0 for the remaining 5. Write down the value of out after each edge.
Hint
Count up three times from 0, then count down five times. Remember that a 3-bit value wraps from 0 to 7 when counting down.
Solution
| Edge | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 |
|---|---|---|---|---|---|---|---|---|
| up_down | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 |
| out | 1 | 2 | 3 | 2 | 1 | 0 | 7 | 6 |
After counting back to 0 at edge 6, the next down count wraps to 7, and then continues to 6. The counter never needs extra logic for this: the 3-bit decrementer naturally produces 111 from 000.
Summary
In this tutorial, you learned:
- Verilog is a hardware description language created in the mid-1980s, standardized as IEEE 1364 and now part of SystemVerilog, and it is used to design ASICs and FPGAs
- Hardware abstraction lets you describe behavior, while synthesis tools work out the gates and the physical implementation
- Verilog differs from software languages because it describes hardware where everything runs in parallel
- Modules with ports are the basic building blocks, and they are combined hierarchically into larger designs
- High-level synthesis, AI tools and newer HDLs are changing chip design, but Verilog knowledge remains essential
Start the series with Introduction to Verilog, then continue with Verilog Syntax and Verilog Modules.
