Verilog is a hardware description language and there is no requirement for designers to simulate their RTL designs to be able to convert them into logic gates. So why do we need to simulate?
Simulation is a technique of applying different input stimulus to the design at different times to check if the RTL code behaves the intended way. Essentially, simulation is a well-followed technique to verify the robustness of the design. It is also similar to how a fabricated chip will be used in the real world and how it reacts to different inputs. For example, the design above represents a positive edge detector with inputs clock and signal which are evaluated at periodic intervals to find the output pe as shown.
There are several EDA companies that develop simulators capable of figuring out the outputs for various inputs to the design. Verilog is defined in terms of a discrete event execution model and different simulators are free to use different algorithms to provide the user with a consistent set of results. The Verilog code is divided into multiple processes and threads and may be evaluated at different times in the course of a simulation.
module tb;reg clk;reg sig;always#5 clk =~clk;// Process loops after every 5nsinitialbegin// Process starts at time 0ns
sig =0;#5 clk =0;// Assign clk to 0 at time 5ns#15 sig =1;// Assign sig to 1 at time 20ns (#5 + #15)#20 sig =0;// Assign sig to 0 at time 40ns (#5 + #15 + #20)#15 sig =1;// Assign sig to 1 at time 55ns (#5 + #15 + #20 + #15)#10 sig =0;// Assign sig to 0 at time 65ns (#5 + #15 + #20 + #15 + #10)#20$finish;// Finish simulation at time 85nsendendmodule