A positive edge detector will send out a pulse whenever the signal it is monitoring changes from 0 to 1 (positive edge).
The idea behind a positive edge detector is to delay the original signal by one clock cycle, take its inverse and perform a logical AND with it's original.
module pos_edge_det (input sig,input clk,output pe);reg sig_dly;always@(posedge clk)begin
sig_dly <= sig;endassign pe = sig &~sig_dly;endmodule
The module shown above is named pos_edge_det and has two inputs and one output. The design aims to detect the positive edge of input sig, and output pe. So we expect to see a pulse on pe whenever sig changes from value 0 to 1.