Ports are a set of signals that act as inputs and outputs to a particular module and are the primary way of communicating with it. Consider a module as a fabricated chip placed on a PCB, and it becomes obvious that the only way to make the chip work is by sending in signals via its pins. Similarly in the Verilog world, ports are used to send and receive signals from the module.

  input  [net_type] [range] list_of_names;
  inout  [net_type] [range] list_of_names;
  output [net_type] [range] list_of_names;
  output [var_type] [range] list_of_names;

It is illegal to use the same name for multiple ports.

  input  aport;         // First declaration - valid
  input  aport;         // Error - already declared
  output aport;         // Error - already declared

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