All procedures in Verilog are placed within one of the following blocks.

  • initial
  • always
  • task
  • function


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The initial block is enabled at the beginning of a simulation at time 0 unit, and will be executed only once during the entire simulation. This block finishes once all the statements within the block are executed. The initial construct need not be scheduled and executed before the always constructs. There are no limits to the number of initial blocks that can be defined inside a module.

  initial [statement]
  initial begin
    [multiple statements]

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