It's always best to get started using a very simple example, and none serves the purpose best other than "Hello World !".

  module tb;
      $display ("Hello World !");

We have a module called tb with no ports and act as the top module for the simulation. The initial block starts at time 0 units, and the first statement will be executed. $display is a Verilog system task used to display a formatted string on to the screen, and cannot be realized into hardware. Hence it's primary use is to help aid in testbench and design debug. In this case, the text message displayed onto the screen is Hello World !.

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