The primary intent of data-types in the Verilog language is to represent data storage elements like bits in a flip-flop and transmission elements like wires that connect between logic gates and sequential structures. Almost all data-types can only have one of the four different values as given below except for real and event data types.
represents a logic zero, or a false condition
represents a logic one, or a true condition
represents an unknown logic value (can be zero or one)