Hardware behavior cannot be implemented without conditional statements and other ways to control the flow of logic. Verilog has a set of control flow blocks and mechanisms to achieve the same.
This conditional statement is used to make a decision about whether certain statements should be executed or not. This is very similar to the if-else-if statements in C. If the expression evaluates to true, then the first statement will be executed. If the expression evaluates to false and if an else part exists, the else part will be executed. The else part of an if-else is optional and can cause a confusion if an else is omitted in a nested if sequence. To avoid this confusion, it's easier to always associate the else to the previous if that lacks an else. Another way is to enclose statements within a begin-end block.
The last else part handles none-of-the-above or default case where none of the other conditions were satisfied.
The case statement is useful to test if an expression matches one of the other expressions in the list and branches accordingly. The default statement is optional and use of multiple default statements is illegal. The expression within parantheses will be evaluated exactly once and matched with the case item in the same order as they are listed within the case block. If one of the case items match then the statements associated with that item will be executed and then exit the case block. If none of the case items match, then the set of statements associated with the default item will be executed if present, else it simply exits the case block without doing anything else.