Lexical conventions in Verilog are similar to C in the sense that it contains a stream of tokens. Its important to note that Verilog is case-sensitive and hence the name var_a is different from var_A. A lexical token may consist of one or more characters and tokens can be comments, keywords, numbers, strings or white space. All lines should be terminated by a semi-colon ;.
White space is a term used to represent the characters for spaces, tabs, newlines and formfeeds, and is usually ignored by Verilog except when it separates tokens. In fact, this helps in the indentation of code to make it easier to read. However blanks(spaces) and tabs (from TAB key) are not ignored in strings.
module dut; // Tokens module (keyword) and dut (identifier)
string name = "Hello!"; // There are 2 spaces in the beginning of this line
string addr = "Earth"; // There is no space in the beginning of this line, but there's a space in the string
There are two ways to write comments in Verilog. A single line comment starts with // and tells Verilog compiler to treat everything after this point to the end of the line as a comment. A multiple-line comment starts with /* and ends with */ and cannot be nested. However, single line comments can be nested in a multiple line comment.
// This is a single line comment
int a; // Creates an int variable called a, and treats everything to the right of // as a comment
This is a
/* This is /*
an invalid nested
block comment */
// this one is okay
// This is also okay
///////////// Still okay