An array declaration of a net or variable can be either scalar or vector. It is a way of creating multi-dimensional objects by specifying an address range after the identifier name. To assign a value to an element of an array, an index for every dimension needs to be given. The index can be an expression and thus gives the ability to reference a particular element based on the values of another variable. An array can be formed for any of the different data-types supported in Verilog.
reg y [11:0];// this is a scalar reg with a depth of 12wire[0:7] y [3:0]// y is an 8-bit vector with a depth of 4integer data [0:10];// data is an array that can store 10 elements
Strings are stored in reg, and the width of the reg variable has to be large enough to hold the string. Each character in a string represents an ASCII value and requires 1 byte. If the size of the variable is smaller than the string, then Verilog truncates the leftmost bits of the string. If the size of the variable is larger than the string, then Verilog adds zeros to the left of the string.
// "Hello World" requires 11 bytesreg[8*11:1] str ="Hello World";// Variable can store 11 bytes, str = "Hello World"reg[8*5:1] str ="Hello World";// Variable stores only 5 bytes (rest is truncated), str = "World"reg[8*20:1] str ="Hello World";// Variable can store 20 bytes (rest is padded with zeros), str = " Hello World"
Memories are digital storage elements that help store a huge amount of information and RAMs, ROMs are good examples of these. Such storage elements can be modeled using one-dimensional arrays of type reg and is called a memory. Each element in the memory may represent a word and is referenced using a single array index.