Sequences are made up of several data items which can be put together in different ways to create interesting scenarios. They are executed by an assigned sequencer which then sends data items to the driver. For example, you could have an agent for the wishbone protocol in place, and the sequencer within the agent can execute sequence items to send transactions across to the design. Hence, sequences make up the core stimuli of any verification plan.

sequences on a sequencer

Here are a few steps to create a user-defined sequence.

  • Derive a sequence from the uvm_sequence base class
  • Use `uvm_object_utils macro to register it with the factory
  • If this sequence should be executed on a particular sequencer, set `uvm_declare_p_sequencer macro
  • Define the body() task with the specific scenario

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