In Register Model, we have seen how to create a model that represents actual registers in a design. Now we'll look at the different components in a register environment required to perform register accesses such as read and write operations.

There are essentially four components required for a register environment :

  • A register model based on UVM classes that accurately reflect values of the design registers
  • An agent to drive actual bus transactions to the design based on some protocol
  • An adapter to convert the read and write statements from the model to protocol based bus transactions
  • A predictor to understand bus activity and update the register model to match the design contents

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