Universal Verification Methodology (UVM) is a standard to enable guaranteed development and reuse of verification environments and verification IP (VIP) throughout the electronics industry. It is a class library defined using the syntax and semantics of System Verilog (IEEE 1800) and is maintained by Accellera. The primary purpose of such a standard is to help companies develop modular, reusable, and scalable testbench structures by providing an API framework that can be deployed across multiple projects.
UVM is mainly derived from Open Verification Methodology (OVM) and is supported by multiple EDA vendors like Synopsys, Cadence, Mentor and Aldec. The UVM class library provides generic utilities like configuration databases, TLM and component hierarchy in addition to data automation features like copy, print, and compare. It brings in a layer of abstraction where every component in the verification environment has a specific role. For example, a driver class object will be responsible only for driving signals to the design, while a monitor simply monitors the design interface and does not drive signals to that interface.
It also goes through many revisions where new features are added and some older ones deprecated. The reference manual for UVM can be obtained here and contains description on class hierarchy, functions and tasks. It might become overwhelming for new users because of the extensive API available for implementation. So, it requires a more disciplined approach to understand the framework part by part. Hopefully, you'll find the information in these pages useful.
It is highly recommended to refresh System Verilog before diving into UVM.
The animation below shows how a typical verification environment is built by extending readily available UVM classes which are denoted by
uvm_* prefix. These components already have the necessary code that will let them connect between each other, handle data packets and work synchronously with others.