What is System Verilog ?

It's a Hardware Verification Language. As you might already know, hardware (computer chips) is designed using a Hardware Description Language (vhdl, verilog) which is then synthesized into gates like NOR, NAND and sequential elements like Flip-Flops. So before you do synthesis, which is a tedious process, you would want to make sure that the functionality aspect of your HDL-constructed design looks good. With System Verilog, you are able to create complex testbench structures and perform simulations to verify the design. You are essentially making sure that the code you have written with verilog functions well and implements features that you intend to.

Why don't you use verilog ?

Back in the 1990's, verilog was the primary language to verify functionality. But then, designs weren't so complex, were smaller and had less features. These days, we are talking of multi-million gate designs with >10 CPU cores, higher RAM and hundreds of IPs. Clearly you need a better language that can deal with the complexity of humungous chips.

What about Vera, e, and other similar HVL ?

Well, they have been in use for some time. System Verilog can be considered an extension of Verilog (the most popular HDL), and it makes sense to verify a Verilog design in System Verilog. Moreover, System Verilog support Object Oriented Programming (OOP) and that alone makes verification of designs at a higher level of abstraction possible.

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