Many digital designs have finite state machines or signals to represent a particular state the design has reached. For example, a traffic light controller can change states from GREEN -> YELLOW -> RED. TO achieve this, there will be a 2-bit state variable of type reg where 00 could represent green, 01 could represent yellow and 10 could represent red. Although this is quite sufficient to be implemented as hardware, it's not so convenient from a verification perspective. If there is a need to debug the design, this state variable will only provide integral values and we have to match this value with the actual representation of the value for it to make sense.


System Verilog solves this problem with the introduction of enumeration. An enumerated type defines a set of named values. In the following example, light is an enumerated variable that can store one of the three possible values. Internally these names are tied with integer values where the first name by default gets 0.

  enum  {RED, YELLOW, GREEN} light1;                 // int type; RED = 0, YELLOW = 1, GREEN = 2
  enum bit[1:0] {RED, YELLOW, GREEN} light2;         // bit type; RED = 0, YELLOW = 1, GREEN = 2
  enum  {RED=3, YELLOW, GREEN} light3;               // RED = 3, YELLOW = 4, GREEN = 5
  enum  {RED = 4, YELLOW = 9, GREEN} light4;         // RED = 4, YELLOW = 9, GREEN = 10 (automatically assigned)
  enum  {RED = 2, YELLOW, GREEN = 3} light5;         // Error : YELLOW and GREEN are both assigned 3
  enum bit[0:0] {RED, YELLOW, GREEN} light6;         // Error: minimum 2 bits are required

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