Module ports and interfaces by default does not specify any timing requirements or synchronization schemes between signals. A clocking block defined between clocking and endcocking does exactly that. It is a collection of signals synchronous with a particular clock and helps to specify the timing requirements between the clock and the signals.

This would allow test writers to focus more on transactions rather than worry about when a signal will interact with respect to a clock. A testbench can have many clocking blocks, but only one block per clock.

  [default] clocking [identifier_name] @ [event_or_identifier]
    default input #[delay_or_edge] output #[delay_or_edge]
    [list of signals]

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