I feel that the answer to the second link doesn't seem complete or right. Most circuits use CMOS technology, and a signal connected to the Vdd enabled by a PMOS transistor should be able to pull it to a level high, either through low-Vt transistors or otherwise the circuit wouldn't work. Even if the signal is connected to a ground, gated by a NMOS transistor would make the signal to get only as low as Vt, which could again vary based on the transistor used and its technology.
Generally there's no good reason inside a chip, since you can have reset generators that start up high or low at power-on. Board-level resets tend to be active low because it's easier to hold a signal low until the power supplies are stable. It also goes back to early bipolar logic that used NAND gates to form flip-flops and therefore it was easier to make control inputs active low.
Inside the chip I tend to make all of my signals active high to reduce mistakes made when trying to DeMorgan logic equations in my head. I suppose it's a matter of preference, though.
There are many reasons behind this, which are directly or indirectly connected to each other. According to me, the basic reason behind this is that mobility of holes is less than electron. So, this is for sure, affects the charging and discharging of the capacitance. Hence, during action of glitches while active_low reset conditions will cause less effect on the reset parameters due to low speed charging and discharging, which delay the time for chip select due to action to low to high level signal (glitch).