A flip-flop captures data at its input at the positive or negative edge of a clock. The important thing to note is that whatever happens to data after the clock edge until the next clock edge will not be reflected in the output. A latch on the other hand, does not capture at the edge of a clock, instead the output follows input as long as the enable pin is asserted.

module d_latch (  input d,
                  input en,
                  input rstn,
                  output reg q);
   always @ (en or rstn or d)
      if (!rstn)
         q <= 0;
         if (en)
            q <= d;

Login to your free account to read more ...

Was this article helpful ?