Uniquely constrain variables

Uniquely constrain variables

One of the most commonly asked questions in System Verilog for interviews is how to uniquely constrain any given array, or any two variables. There are a couple of workarounds for this, but we didn't have a clean shortcut to achieve this very useful functionality until the 2012 IEEE revision.

The unique keyword allows a group of variables to be constrained in such a way so that no two variables have the same value after randomization. However a few limitations involve cases where no randc variable can be included, scalar variables should be of integral type and only unpacked arrays whose leaf element is integral. Obviously the minimum number of variables that unique can work on is two. Let's look at an example next.

class myClass;
   rand bit [3:0] array [10];
   rand bit [7:0] count;
   rand bit [1:0] mode;
   constraint c_unique1 { unique {array}; };
   constraint c_unique2 { unique {count[1:0], mode}; };
   function void display ();
      $display ("Count = 0x%0h \nMode = 0x%0h", count, mode);
      foreach (array[i])
         $display ("array[%0d] = %0d", i, array[i]);
module tb;
   myClass cls;
   initial begin
      cls = new ();
      cls.display ();
Simulation Log
ncsim> run
Count = 0xad
Mode = 0x3
array[0] = 15
array[1] = 13
array[2] = 12
array[3] = 4
array[4] = 7
array[5] = 5
array[6] = 0
array[7] = 6
array[8] = 1
array[9] = 11
ncsim: *W,RNQUIE: Simulation is complete.
`uvm_create 'd name of an object
how to randomize selected variables only

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Tuesday, 20 March 2018